M2M-PCI64A Universal, 64/32-bit, 66/33MHz, Myrinet-SAN/PCI interface |
| An improved M3M-PCI64B product replaced this product on Myricom's standard-product list in July 2000. |
These universal, 64/32-bit, 66/33MHz, Myrinet-SAN/PCI interfaces are ideal for the most demanding cluster and distributed-computing applications. The interface provides more than 1 GByte/s of local-memory data rate, a fast RISC to execute the Myrinet control program, a versatile DMA controller to support zero-copy APIs, and a complete set of high-availability and data-integrity features.
Block diagram
Software Support. All Myricom software support for the PCI64 family of interfaces is based on the GM Myrinet Control Program and the GM API. Software support is available now for:
MPICH over GM is also available now.
PCI-bus Interface: 64/32-bit, 66/33MHz, supports all burst modes and write-invalidate, master or slave. These interfaces are capable of sustained PCI data rates approaching the limits of the PCI bus (528 MB/s for 64-bit, 66MHz; 264 MB/s for 64-bit, 33MHz or 32-bit, 66MHz; 132 MB/s for 32-bit, 33MHz). However, the data rate to/from system memory will depend upon the host's memory and PCI-bus implementation. These interfaces function correctly in all PCI slots that are compliant with PCI specifications version 2.1 or later, with either 3.3V or 5V PCI-bus signal levels. (3.3V signaling is required of 66MHz PCI slots, but 33MHz PCI slots may use either 5V or 3.3V signaling.) PCI parity generation and detection is provided. The interface provides a 64-bit Base Address Register (BAR), but will also function properly when programmed with a 32-bit address, per the PCI specifications. A mechanical switch on the circuit board allows switching to a 32-bit BAR to accommodate operating systems and firmware that either cannot properly load a 64-bit address into a 64-bit BAR, or cannot correctly write a 32-bit address into a 64-bit BAR.
DMA controller: Traverses multiple lists in the interface's local memory to initiate DMA transfers, thus allowing multiple pending DMA operations. In order to support zero-copy APIs efficiently, the DMA operations can be performed with arbitrary byte counts and byte alignments. The DMA controller computes the IP checksum for each transfer. The DMA controller also provides a "doorbell" signalling mechanism that allows the host to write anywhere within the doorbell region, and have the address and data stored in a FIFO queue in the local memory.
Interface processor: LANai 7 RISC operating at up to 66MHz (1x or 2x the PCI clock, depending on the PCI-bus frequency). Note: the RISC in the LANai 7 is similar to but is not binary-compatible with earlier LANai RISCs.
Local memory: 2MB (256Kx8B) in the -2 versions; 4MB (512Kx8B) in the -4 versions. The local memory operates at 2x the processor-clock rate, i.e., at 132 MHz with a 66MHz processor clock. Up to 1,056 MB/s of memory bandwidth is available to support the Myrinet link, the host DMA, and the RISC processor. Byte parity is generated and checked.
Myrinet-SAN port: 1.28+1.28 Gb/s data rate on the A link; B link unused.
Physical characteristics: ~5 Watts from the 5V PCI power. PCI Short Card.
Myricom-supported software: Open source, distributed from the Myrinet Software & Customer Support page. These interfaces require the use of the GM software; the MyriAPI software is not available for the PCI64 family of interfaces.
Programmer's Documentation for customers who write their own Myrinet control programs.
M2M-PCI64A-2 Universal Myrinet-SAN/PCI Interface
Last updated: 1 July 2000