M3M-PMC64B & M3M-PMC64C Universal, 64/32-bit, 66/33MHz, Myrinet-SAN/PCI interface |
These universal, 64/32-bit, 66/33MHz, Myrinet-SAN/PCI interfaces are functionally identical to the M3M-PCI64B & C interfaces, but are in the PCI-Mezzanine-Card (PMC) form factor. The interface includes a fast RISC to execute the Myrinet control program, a versatile DMA controller to support zero-copy APIs, and a complete set of high-availability and data-integrity features. The difference between the PMC64B and PMC64C interfaces is the allowed clock rate of the RISC and local memory: 133MHz for the PMC64B, and 200MHz for the PMC64C.
Block diagram
PCI-bus Interface: 64/32-bit, 66/33MHz, supports all burst modes and write-invalidate, master or slave. These interfaces are capable of sustained PCI data rates approaching the limits of the PCI bus (528 MB/s for 64-bit, 66MHz; 264 MB/s for 64-bit, 33MHz or 32-bit, 66MHz; 132 MB/s for 32-bit, 33MHz). However, the data rate to/from system memory will depend upon the host's memory and PCI-bus implementation. These interfaces function correctly in all PCI slots that are compliant with PCI specifications version 2.2 or later, with either 3.3V or 5V PCI-bus signal levels. (3.3V signaling is required of 66MHz PCI slots, but 33MHz PCI slots may use either 5V or 3.3V signaling.) PCI parity generation and detection is provided. The interface provides a 64-bit Base Address Register (BAR), but will also function properly when programmed with a 32-bit address, per the PCI specifications.
DMA controller: Traverses multiple lists in the interface's local memory to initiate DMA transfers, thus allowing multiple pending DMA operations. In order to support zero-copy APIs efficiently, the DMA operations can be performed with arbitrary byte counts and byte alignments. The DMA controller computes the IP checksum for each transfer. The DMA controller also provides a "doorbell" signalling mechanism that allows the host to write anywhere within the doorbell region, and have the address and data stored in a FIFO queue in the local memory.
Interface processor: LANai 9 RISC operating at up to 133MHz for the PMC64B interfaces, or at up to 200MHz for the PMC64C interfaces. Note: the RISC in the LANai 9 is similar to but is not binary-compatible with earlier LANai RISCs.
Local memory: 2MB (256Kx8B) in the -2 version; 4MB (512Kx8B) in the -4 version. The local memory operates from the same clock as the RISC, i.e., at up to 133 MHz for the PCI64B interfaces, or at up to 200MHz for the PCI64C interfaces. Up to 1,067 MB/s (PCI64B) or 1,600 MB/s (PCI64C) of memory bandwidth is available to support the Myrinet port, the host DMA, and the RISC processor. Byte parity is generated and checked.
Myrinet-SAN port: The default data rate
can be switched between SAN-2000 (2.0+2.0 Gb/s) and SAN-1280 (1.28+1.28
Gb/s) with a mechanical switch on the circuit board. The host can over-ride
the default data rate. The SAN port appears on the A
link of the SAN connector; the B link is unused.
Physical characteristics: ~4 Watts from the 3.3V PCI power. PCI Mezzanine Card (IEEE P1386.1). Note: The PMC specifications require that 3.3V power be available, and this component operates from the 3.3V power.
Myricom-supported software: Open source, distributed from the Myrinet Software & Customer Support page. These interfaces require the use of the GM software; the MyriAPI software is not available for the PCI64 family of interfaces.
Programmer's Documentation for customers who write their own Myrinet control programs.
M3M-PMC64B-2
Last updated: 25 July 2001