Open Specifications
and Documentation

Myrinet® and Myricom® are registered trademarks of Myricom, Inc.

Myrinet is an American National Standard: ANSI/VITA 26-1998, "Myrinet-on-VME Protocol Specification." This standard was developed under VITA auspices. VITA is the VMEbus International Trade Association; hence, the "Myrinet-on-VME" title for the specification. However, the same specifications apply to all Myrinet components.

For convenience, a duplicate of the VITA Standards Organization final draft (1.1) specification is available here (PDF 151KB). In this specification, the definition of Myrinet at the Data Link level (level 2 in the ISO reference model for computer networks) preceeds the specifications that govern the SAN-1280 and LAN-1280 (1280+1280 Mbit/s link) implementations at the Physical level (level 1).

In July 2000, after the publication of the ANSI Standard, Myricom introduced third-generation (M3) "Myrinet-2000" products with 2000+2000 Mbit/s links. In order to converge with industry-standard 2.5GBaud 8b/10b-encoded serial links, which have a data rate of 2000 Mbits/s, Myricom decided to use 2000 Mbits/s rather than 2560 Mbits/s as the base for this generation of Myrinet. The SAN-2000 Physical level (PHY) is an interpolation of the SAN-1280 and SAN-2560 PHYs described in the ANSI standard. 2.5GBaud 8b/10b-encoded serial links over copper cables (M3S, up to 10m) or over fiber (M3F, up to 200m) are the successors to the LAN-1280 links. The specification for the PHY for the serial links is available here (PDF 60KB).

Myrinet Packet Types

The first 16 bits of every Myrinet packet (after the routing bytes) should consist of a registered Myrinet packet type, so that multiple protocols can exist on a single Myrinet. Myricom maintains the Myrinet-packet-type registry.

Myricom Custom-VLSI Chips

An index to the specifications and documentation for Myricom's custom-VLSI chips is at http://www.myri.com/vlsi/.

Myrinet-2000 Switch Line Card
Interface and Packaging Specifications

Myricom treats the interface and packaging specifications of its Myrinet-2000 switch line cards as open. See http://www.myri.com/open-specs/switch-line-card/.

Historical Notes

The original Myrinet specification for first-generation Myrinet implementations, written in 1994 and updated in 1995, is available for reference and possible historical interest. It is accurate for second-generation Myrinet components with respect to the Link-level and LAN-Physical-level specifications, except:

• The FRES control symbol was eliminated in second-generation Myrinet components. Instead, both input and output ports have long-period timeouts.
• Second-generation LAN links now operate preferentially at LVDS (Low-Voltage-Differential-Signaling) voltage levels (a 1.2V center voltage and a 400mV swing) rather than Pseudo-ECL levels.
• Second-generation LAN links operate at 160+160 MBytes/s up to ~35 feet. The center pin of the DB-37 connector is used to program the data rate, either 80+80 MBytes/s or 160+160 MBytes/s, depending on the cable length.

The other significant change in Myrinet between the first- and second-generation implementation was the addition of the SAN links at the Physical level. The SAN links differ from LAN links in employing low-voltage (1.2V) single-ended signaling rather than balanced-differential signaling; and in using a separate, backward-directed, flow-control signal.

Last modified: 4 February 2002