(c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 1 ============================================================================== LANai 3.1 0. INTRODUCTION The LANai 3.1 chip is a programmable communication device that provides an interface to the Myrinet local area network. As illustrated in Figure 1, the LANai 3.1 chip consists of the LANai core, with an instruction-interpreting processor and a packet interface, the Myrinet-link interface, the memory interface, and a DMA/Checksum engine. Myrinet ^ | + - - - - - - - - - - - - - - - - | - - - - | - - - - + | v | +---------------+ | | | | | Myrinet-Link | | +---------->| Interface | | | +---------| | | | | +---------------+ | | | ^ | | +---------------|-|------------|---------|------+ | | | v | v | | | +---------------+ +---------------+ | | | | | | | | | | | Processor |------>| Packet | | | | | |<------| Interface | | | | | | | | | | | +---------------+ +---------------+ | | | | ^ ^ ^ | | | | | | | | | | | | v v | | | | | <=================================> | | | | | ^ | | | | | | LANai core | | +-----|-|--------------------|------------------+ | | | | | v | | | +---------------+ | | | | /| | | | DMA/Checksum |----> / | | | | Engine |<---- / |<=+ | | | / | | +---------------+ | | | ^ | / | LBUS <=============+===========>| | Memory Interface | | \ | | | | \ | | \ |<==========================> EBUS | \ | | \| | | +- - - - - - - - - - - - - - - - - - - - - - - - - - -+ Figure 1: The LANai 3.1 chip (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 2 ============================================================================== 0.1 LANai 3.1 processor This specification describes only the network-related features of the LANai 3.1 processor; for instruction-set details, consult the LANai 3.1 Instruction Set specification. The LANai processor is a 32-bit dual-context machine, with 24 general-purpose registers. One context is interruptable, and we shall refer to it as the `user' context. An interrupt during the execution of the user context causes the processor to switch to the other, `system', context. The system context is not interruptable. The system context transfers execution to the user context by executing the `punt' assembly instruction (see LANai 3.1 Instruction Set specification). Executing the `punt' instruction in the user context similarly switches execution to the system context. Upon reset, the LANai processor begins executing code in the system context, starting from address 0. The three special registers that control interrupt generation are described in detail in Section 7. They are: the Interrupt Status Register (ISR), the Interrupt Mask Register (IMR), and the External Interrupt Mask Register (EIMR). When a bit of ISR is equal to 1 and the corresponding bit in the IMR is equal to 1, an interrupt request is asserted for the on-chip processor. When a bit of ISR is equal to 1 and the corresponding bit of EIMR is equal to 1, the interrupt output pin of the LANai 3.1 chip is asserted (see the applicable Myrinet-computer-interface specification for details on external interrupts). The remainder of the special-purpose registers are used for data communication and are described in this specification. (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 3 ============================================================================== 0.2 Memory Interface In the remainder of this specification, we shall refer to 8-bit data units as bytes, to 16-bit units as half-words, and to 32-bit units as words. Although the internals of the LANai 3.X series of chips support 32-bit addresses, pin-count limitations restrict the LBUS of the LANai 3.1 chip to a maximum of 128K bytes. The LBUS operates at twice the chip-clock speed --- there are two memory cycles for every clock cycle. The external-access bus (EBUS), the packet- interface receive DMA, and the packet-interface send DMA each request a maximum of one memory access per clock cycle. The on-chip processor requests up to two memory accesses per clock cycle (instruction and data). The two memory cycles within each clock cycle are assigned based on the following priority (highest to lowest): EBUS, receive DMA, send DMA, and the processor. Since every EBUS memory request is granted, the LANai 3.1 chip along with the memory on its LBUS appears as a block of memory when observed from the EBUS. The word and half-word memory accesses on the LBUS must be aligned; any least- significant bits of an address that would make a memory access non-aligned are ignored. Both the LBUS and the EBUS addresses are byte addresses, and the byte order is big-endian (the most significant byte of a word is stored at the lowest byte address). Although the LANai core cannot access the EBUS directly, the on-chip processor can initiate a data transfer between the LBUS and the EBUS (Section 3). 0.3 Data Communication The LANai 3.1 chip provides the programmer with bidirectional access to the Myrinet network. A data-communication, flow-control unit is called a flit, and consists of eight data bits plus a tail bit. Packets are of arbitrary length (in flits), and the tail bit marks the last flit of every packet. The byte order in the communication network is big-endian, i.e., the most significant byte of a word (or of a half-word) appears first in the network. Packets are injected into the network and consumed off of the network by the packet interface. The packet interface is controlled by accessing special, memory-mapped registers, described in the remainder of this specification. 0.4 Special, Memory-Mapped Registers All the packet-interface control registers and interrupt control registers (except for the IMR and the EIMR) are memory-mapped and can be accessed by the LANai core and from the EBUS. The IMR is an internal register of the LANai 3.1 on-chip processor and is not accessible from the EBUS. The EIMR is memory-mapped, but it is accessible only from the EBUS. When accessing the special, memory-mapped registers, the regular memory arbitration mechanism described in Section 0.2 applies. The mutual exclusion at any higher level is the responsibility of the programmer. (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 4 ============================================================================== 1. PACKET SENDING An outgoing packet is produced by writing into the following 32-bit special registers: SB (Send Byte) --- appends to the outgoing packet the least significant byte of the value written into SB. SH (Send Half-Word) --- appends to the outgoing packet the least significant half-word written into SH (high-order byte first). SW (Send Word) --- appends to the outgoing packet the word written into SW (most significant byte first). ST (Send Tail) --- writing a 0 into ST completes the outgoing packet by appending a tail flit with its data field equal to the cyclic-redundancy-check (CRC-8) byte for that packet. SML (Send Memory Limit) --- initiates a send-DMA transfer that appends to the outgoing packet, one word at a time, the contents of the memory buffer that starts at SMP and ends at SML (it is not possible to specify a zero-length buffer). SMLT (Send Memory Limit, --- the same as SML, and, in addition, completes with the Tail) the outgoing packet by appending a tail flit with its data field equal to the CRC-8 byte for that packet. SMP (Send Memory Pointer) --- specifies the beginning of the send-DMA memory buffer. This register is incremented by four by the packet interface as each word is appended to the outgoing packet, and, upon completion, equals SML+4. SA (Send Align) --- the two least-significant bits of this register specify how many leading flits (0-3) of the contents of the next-specified send-DMA memory buffer should NOT be appended to the outgoing packet. Only the first send-DMA transfer following a write into this register is affected. See Section 7 for information on how the completion of a send-DMA transfer can be detected. Since the send-DMA transfer specified by the SMP and SML accesses 32 bits at a time, the send memory buffer must be aligned on a word boundary. Hence, the two least significant bits of SMP and the two least significant bits of SML(T) are hard-wired to zero. SB, SH, SW, ST, and SA are not physical storage registers, and reading any of them is a programming error. Reading SMP and SML(T) are valid operations, but one should note that SML and SMLT are stored in the same physical register. Writing any of the send registers during a send-DMA transfer is a programming error (Section 7). (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 5 ============================================================================== 2. PACKET RECEIVING An incoming packet is accepted from the network by accessing the following special registers: RB (Receive Byte) --- reading RB, an 8-bit special register, consumes one byte off of the incoming packet. RH (Receive Half-Word) --- reading RH, a 16-bit special register, consumes one half-word off of the incoming packet (the first byte consumed becomes the most significant one). RW (Receive Word) --- reading RW, a 32-bit special register, consumes one word off of the incoming packet (the first byte consumed becomes the most significant one). RML (Receive Memory Limit) --- writing into RML, a 32-bit special register, enables a receive-DMA transfer and instructs the packet interface to put the (remainder of the) incoming packet, one word at a time, into the memory buffer that starts at RMP and ends at RML (it is not possible to specify a zero-length buffer). RMP (Receive Memory Pointer) --- a 32-bit special register, specifies the beginning of the receive-DMA memory buffer. This register is incremented by four by the packet interface as each word is written into the buffer. After an entire packet has been received, RMP points to the first word past the end of the packet, unless the buffer has been exhausted (Section 7). See Section 7 for information on how the completion of a receive-DMA transfer can be detected. Since the receive-DMA transfer specified by the RML and RMP accesses 32 bits at a time, the receive memory buffer must be aligned on a word boundary. Hence, the two least significant bits of RML and the two least significant bits of RMP are hard-wired to zero. Upon receipt, any packet with a non-zero tail flit has failed a cyclic redundancy check (CRC-8). This should be checked in software after the packet has been received. It is possible to read past the tail flit of the incoming packet (with RH, RW, or with receive DMA). In such cases, the packet following the currently accessed packet is guaranteed not to be corrupted. However, the bytes corresponding to the flits past the tail flit are undefined (Section 7). RB, RH, and RW are not physical storage registers, and writing any of them is a programming error. Reading RMP or RML is a valid operation. Initiating any receive operation during a receive-DMA transfer is a programming error (Section 7). (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 6 ============================================================================== 3. EBUS-LBUS DATA TRANSFER In the typical operating regime, the LANai 3.1 chip operates as a slave device on the EBUS. In this regime, the LANai 3.1 chip along with the memory on its LBUS appears as a block of memory when observed from the EBUS. The LANai 3.1 chip incorporates a DMA engine that can be programmed to perform data transfer between the LBUS and the EBUS, and, in this regime only, the chip acts as a master on the EBUS. The LANai EBUS interface is simple and generic, and extra hardware is necessary to connect it to any standard bus. Consult the applicable Myrinet-computer-interface specification for details. The EBUS-LBUS DMA engine is controlled by the following 32-bit, special registers: LAR (LBUS Address Register) --- points to the beginning of the DMA buffer on the LBUS. This register is incremented by four as each word is transferred, and, upon completion, points to the first word past the LBUS DMA buffer. EAR (EBUS Address Register) --- points to the beginning of the DMA buffer on the EBUS. This register is incremented by four as each word is transferred, and, upon completion, points to the first word past the EBUS DMA buffer. DMA_DIR (DMA Direction) --- the least-significant bit of this register controls the direction of the EBUS-LBUS DMA transfer. 1: EBUS -> LBUS 0: LBUS -> EBUS DMA_CTR (DMA Counter) --- a non-zero value of the DMA_CTR register initiates the DMA transfer. This register is decremented by four as each word is transferred, and equals 0 upon completion. DMA_STS (DMA Status) --- this register contains EBUS-specific information. For details, consult the applicable Myrinet-computer-interface specification. See Section 7 for information on how the completion of an EBUS-LBUS DMA transfer can be detected. Since the EBUS-LBUS DMA transfers 32 bits at a time, the LBUS memory buffer must be aligned on a word boundary. Hence, the two least significant bits of LAR and the two least significant bits of DMA_CTR are hard-wired to zero. DMA_DIR and DMA_STS are write-only registers, and reading either of them is a programming error. Reading LAR, EAR, or DMA_CTR is a valid operation. Writing any of the registers listed above during an EBUS-LBUS DMA transfer is a programming error (Section 7). (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 7 ============================================================================== 4. INTERNET-CHECKSUM COMPUTATION The LANai 3.1 chip includes a mechanism to compute a partial Internet checksum. The partial checksum is stored in the CKS (ChecKSum) register. This register is modified as a side effect of the EBUS-LBUS DMA transfers. Upon completion of an EBUS-LBUS DMA transfer (Section 7), the CKS register contains the result of the 32-bit, 1's-complement addition of its initial value and the values of all transferred data items (the DMA engine transfers 32-bit data items only). A typical 16-bit-Internet-checksum computation consists of: writing zero into CKS; performing one or more EBUS-LBUS DMA transfers; and, then adding the most and least significant half-word of CKS (in software) using 1's complement addition. (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 8 ============================================================================== 5. TIMERS/COUNTERS There are two real-time counters on the LANai 3.1 chip, both of which use the time reference that is equal to 40 times the period of the clock of the Myrinet-link interface. Nominally, this is a 40 MHz clock, so the time reference is equal to 1 microsecond. 5.1 The Real-Time Clock The RTC special register is a 32-bit counter that is incremented every time-reference period. 5.2 The Interrupt Timer The IT special register is a 32-bit counter that is decremented every time-reference period. Whenever this counter makes a transition from 0 to -1, a timer interrupt occurs. Whenever it makes a transition from -2^31 to +2^31-1, a watchdog interrupt occurs. See Sections 0.1 and 7 for information on interrupt handling. (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 9 ============================================================================== 6. MISCELLANEOUS SPECIAL REGISTERS Upon reset (Section 8) or an open-link timeout (Section 7), the Myrinet-link interface is held in the reset state until activated. ACTIVATE --- writing to the ACTIVATE special register activates the Myrinet- link interface (see Section 8). Some versions of the LANai chip and of computer interfaces require configuration before use. For correct configuration, consult the applicable Myrinet-computer-interface specification. VERSION --- writing to the VERSION special register configures the Myrinet- link interface. MYRINET --- the three least-significant bits of the MYRINET special register are: STOP_GO_ENABLE - the Myrinet-link interface can operate in a mode in which the STOP and GO Myrinet-link control symbols are ignored (see Myrinet Link Specifications). A value 1 in the least-significant bit (bit 31) of the MYRINET special register instructs the Myrinet-link interface to observe the STOP-GO protocol. FRES_ENABLE - upon receipt of an FRES Myrinet-link control symbol the fres_int bit of ISR is set (see Section 7). A value 1 in the bit 30 of the MYRINET special register instructs the Myrinet-link interface to reset the LANai chip when an FRES is received. CRC_ENABLE - as discussed in Sections 1 and 2, the packet interface completes every outgoing packet with the CRC-8 byte, and verifies the CRC-8 byte for every incoming packet. The tail flit contains the CRC-8 byte only if the bit 29 of the MYRINET special register is 1. When this bit is 0, the tail, CRC flit of every outgoing packet is set to 0, and no CRC verification is performed on the incoming packets. To facilitate network-fault recovery, the LANai 3.1 can inject the FRES Myrinet-link control symbol (see Myrinet Link Specifications) into the Myrinet network. FRES --- writing to the FRES special register injects the FRES control symbol into the Myrinet network. There is one additional special register that can be used by the programmer to modify the value of a dedicated LANai 3.1 output pin. The name of this pin is only suggestive of its actual usage which is described in detail in the applicable Myrinet-computer-interface specification. LED --- the least-significant bit of the special register LED is driven to the LED output pin. The special registers described in this section are write-only registers, and reading any of them is a programming error. (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 10 ============================================================================== 7. STATUS OF THE PACKET INTERFACE The ISR bits with the _sig (signal) postfix are included for simple host-LANai communication. A signal bit can be set only by the LANai processor and reset only from the EBUS, or vice versa. The ISR bits with the _rdy (ready) postfix are maintained by the packet interface, and cannot be modified by the processor. However, when such a bit becomes 1, the packet interface may reset it only as a result of a bit-specific, processor-initiated request to the packet interface, as described later in this section. Please read the warning about the timing of the clearing of _rdy bits at the end of this section. The ISR bits with the _int (interrupt) postfix are set by the packet interface when their corresponding events occur. These bits can be reset directly --- by writing a 1 into them, or indirectly --- in a bit-specific way. Please read the warning about the timing of the bit-specific clearing of _int bits at the end of this section. The information on the status of the packet interface is kept in the Interface Status Register (ISR), which consists of the following bits (bit 0 is the most significant): bit# : 0 1 2 3 4 5 6 7 value: 1 host 0 0 0 0 0 0 _sig bit# : 8 9 10 11 12 13 14 15 value: lan7 lan6 lan5 lan4 lan3 lan2 lan1 lan0 _sig _sig _sig _sig _sig _sig _sig _sig bit# : 16 17 18 19 20 21 22 23 value: word half send link fres wake orun2 orun1 _rdy _rdy _rdy _int _int _int _int _int bit# : 26 25 26 27 28 29 30 31 value: tail wdog time dma send buff recv byte _int _int _int _int _int _int _int _rdy Bit 0 of ISR is also referred to as the dbg_bit. This bit is always equal to 1, and can be used for single-stepping the code that runs in user context (see LANai 3.1 Instruction Set specification). host_sig --- this bit is set when the LANai processor writes a 1 into it, and reset when a 1 is written into it from the EBUS. Bits 2 through 7 are always equal to 0 and are reserved for future expansion. lan7_sig ... lan0_sig --- each of these bits is set when a 1 is written into it from the EBUS, and reset when the LANai processor writes a 1 into it. (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 11 ============================================================================== send_rdy --- this bit is maintained by the packet interface, and it denotes that the outgoing channel is not blocked, so that an SB, SH, SW, or an ST operation can be issued. Writing SB, SH, SW, or ST while this bit is equal to 0 is a programming error, and may corrupt the outgoing packet. During a send-DMA operation (from the time when the SML(T) is written until the time when send_int becomes one), send_rdy is equal to 0 regardless of the state of the outgoing channel. This bit cannot be modified by the processor. The value of the send_rdy bit does not affect the validity of send-DMA operations (writing SMP and SML(T)). byte_rdy --- this bit is maintained by the packet interface and is equal to 1 if there is at least one flit on the incoming channel, indicating that an RB operation can be issued. Reading RB while the byte_rdy bit is equal to 0 is a programming error, and may corrupt the incoming packet. During a receive-DMA operation (from the time when the RML is written, until the time when recv_int or buff_int becomes one), this bit is equal to 0 regardless of the state of the incoming channel. This bit cannot be modified by the processor. half_rdy --- this bit is maintained by the packet interface and is equal to 1 if: (1) there are at least two flits of the same packet on the incoming channel, or (2) the next available flit on the incoming channel is a tail. In either case, the half_rdy bit indicates that an RH operation can be issued. Reading RH while the half_rdy bit is equal to 0 is a programming error, and may corrupt the incoming packet. During a receive-DMA operation (from the time when the RML is written, until the time when recv_int or buff_int becomes one), this bit is equal to 0 regardless of the state of the incoming channel. Note that half_rdy=1 implies byte_rdy=1. However, because of (2), half_rdy=1 does not imply that two RB operations can be issued. This bit cannot be modified by the processor. word_rdy --- this bit is maintained by the packet interface and is equal to 1 if: (1) there are at least four flits of the same packet on the incoming channel, or (2) the first, the second, or the third available flit on the incoming channel is a tail. In either case, the word_rdy bit indicates that an RW operation can be issued. Reading RW while the word_rdy bit is equal to 0 is a programming error, and may corrupt the incoming packet. During a receive-DMA operation (from the time when the RML is written, until the time when recv_int or buff_int becomes one), this bit is equal to 0 regardless of the state of the incoming channel. Note that word_rdy=1 => half_rdy=1 => byte_rdy=1. However, because of (2), word_rdy=1 does not imply that, for example, two RH operations can be issued. This bit cannot be modified by the processor. The values of byte_rdy, half_rdy, and word_rdy bits do not affect the validity of receive-DMA operations (writing RMP and RML). (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 12 ============================================================================== recv_int --- this bit is set by the packet interface to signal the completion of a receive-DMA transfer, i.e., when an entire incoming packet has been transferred into the receive memory buffer. This bit is cleared by the processor, either directly --- by writing a 1 into it ---, or indirectly --- when RML is written. After a receive-DMA operation is initiated, one must not initiate any receive operation until the recv_int bit, the buff_int bit, or both, become 1. buff_int --- this bit is set by the packet interface when the receive-DMA buffer has been exhausted (the last word written is at the location pointed to by RML, and RMP=RML+4). This bit is cleared by the processor, either directly --- by writing a 1 into it ---, or indirectly --- when RML is written. After a receive-DMA operation is initiated, one must not initiate any receive operation until the recv_int bit, the buff_int bit, or both, become 1. send_int --- this bit is set by the packet interface to signal the completion of a send-DMA transfer, i.e., when the contents of the memory buffer specified by SMP and SML(T) have been appended to the outgoing packet. This bit is cleared by the processor, either directly --- by writing a 1 into it, or indirectly --- when SML(T) is written. After a send-DMA operation is initiated, one must not initiate any send operation until the send_int bit becomes 1. tail_int --- this bit is set by the packet interface when an RB, an RH, or an RW operation consumes a tail flit. This bit is cleared by the processor, either directly --- by writing a 1 into it ---, or indirectly --- when another RB, RH, or RW operation is issued. orun1_int, orun2_int --- these bits are set by the packet interface when an overrun condition is detected, i.e., when a receive operation reads past the tail flit of a packet. The two bits taken together represent the number of flits read past the tail flit (0 through 3). For example, if when using receive DMA (RMP and RML), the tail is received in the most-significant byte of a 4-byte word, both orun2_int and orun1_int will be set, indicating that the values of the 3 least significant flits are undefined. These bits are cleared by the processor, either directly --- by writing a 1 into them ---, or indirectly --- when any receive operation is initiated. Regardless of the unit of data transfer for packet receiving, after the whole packet has been received the overrun conditions should be tested. Although one may make simplifying assumptions about packet lengths and thereby eliminate the need for overrun check, this approach relies on a guarantee that the communication network is error-free. (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 13 ============================================================================== wake_int --- this bit is set when the WAKE input pin is driven high. The actual usage of this pin is described in detail in the applicable Myrinet-computer-interface specification. This bit is cleared by the processor, only directly --- by writing a 1 into it. time_int --- this bit is set by the interrupt timer whenever it makes a transition from 0 to -1. This bit is cleared by the processor, either directly --- by writing a 1 into it, or indirectly --- when IT is written. wdog_int --- this bit is set by the interrupt timer whenever it makes a transition from -2^31 to +2^31-1. This bit is cleared by the processor, either directly --- by writing a 1 into it, or indirectly --- when IT is written. dma_int --- this bit is set by the EBUS-LBUS DMA engine when the DMA_CTR reaches 0 to signal the completion of a DMA transfer. This bit is cleared by the processor, either directly --- by writing a 1 into it ---, or indirectly --- when the DMA_CTR is written. After an EBUS-LBUS DMA operation is initiated, one must not initiate another such operation until the dma_int bit becomes 1. link_int --- this bit is set by the receive section of the on-chip Myrinet-link interface whenever it generates the open-link timeout (see Myrinet Link Specifications). This bit is cleared by the processor, only directly --- by writing a 1 into it. fres_int --- this bit is set by the receive section of the on-chip Myrinet- link interface whenever it receives the FRES control symbol (see Myrinet Link Specifications). The receipt of the FRES control symbol is considered catastrophic and indicates the LANai's failure to consume the incoming message. On receipt of this symbol, the fres_int bit is set, and, if the FRES_ENABLE bit of the MYRINET special register is 1, the LANai chip is reset. By examining the fres_int bit, one can distinguish between the reset-pin-induced and FRES-induced reset. This bit is cleared by the processor, only directly --- by writing a 1 into it. (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 14 ============================================================================== WARNING: Because the special registers are memory-mapped, and because the LANai processor is a pipelined machine, there is a delay between the time of a special-register access and the time of the change of of the corresponding ISR bit(s). In case of tight polling loops, this delay can result in a race condition, whereby the program could, for example, misinterpret a not-yet-cleared ISR _int bit for an indication of a new event. The following table illustrates how special-register accesses affect ISR bits. A number in the table specifies for how many assembly instructions following the special-register-read-or-write instruction the ISR bit is undefined. clr - always cleared set - always set clr? - potentially cleared set? - potentially set +----------------+---------+---------+---------+---------+---------+---------+ | | write | write | read |write SB,| write | write | | | RML |SML,SMLT |RB,RH,RW |SH,SW,ST | IT | DMA_CTR | +----------------+---------+---------+---------+---------+---------+---------+ | send_rdy clr | | 2 | | | | | +----------------+---------+---------+---------+---------+---------+---------+ | send_rdy clr? | | | | 3 | | | +----------------+---------+---------+---------+---------+---------+---------+ | byte_rdy\ | | | | | | | | half_rdy >clr | 2 | | | | | | | word_rdy/ | | | | | | | +----------------+---------+---------+---------+---------+---------+---------+ | byte_rdy\ | | | | | | | | half_rdy >clr? | | | 3 | | | | | word_rdy/ | | | | | | | +----------------+---------+---------+---------+---------+---------+---------+ | send_int clr | | 1 | | | | | +----------------+---------+---------+---------+---------+---------+---------+ | recv_int\ | | | | | | | | buff_int/ clr | 1 | | | | | | +----------------+---------+---------+---------+---------+---------+---------+ | orun1_int\ | | | | | | | | orun2_int/clr | 1 | | 1 | | | | +----------------+---------+---------+---------+---------+---------+---------+ | orun1_int\ | | | | | | | | orun2_int/set? | | | 3 | | | | +----------------+---------+---------+---------+---------+---------+---------+ | tail_int clr | | | 1 | | | | +----------------+---------+---------+---------+---------+---------+---------+ | tail_int set? | | | 3 | | | | +----------------+---------+---------+---------+---------+---------+---------+ | time_int\ | | | | | | | | wdog_int/ clr | | | | | 1 | | +----------------+---------+---------+---------+---------+---------+---------+ | dma_int clr | | | | | | 1 | +----------------+---------+---------+---------+---------+---------+---------+ (c)1994 Myricom, Inc., LANai 3.1, 20 September 1995 - PROPRIETARY page 15 ============================================================================== 8. INITIALIZATION The Myrinet-link interface of the LANai 3.1 chip is clocked by its own, separate, link clock, completely independent of the clocking of the rest of the chip. Clock for the non-Myrinet-link part of the LANai 3.1 chip (processor, packet interface, EBUS DMA engine) is typically derived from the clock of the I/O bus connected to the EBUS. While the LANai 3.1 chip is in reset, the circuitry that generates the on-chip clock must be initialized through the EBUS. For details, consult the applicable Myrinet-computer-interface specification. After chip reset, the on-chip processor begins executing code in the system context, starting from the address 0. The state of the fres_int bit in the ISR upon reset indicates whether the reset has been a regular, reset-pin initialization (0), or an FRES-induced reset (1). All the remaining bits of ISR are equal to 0, except the dbg_bit and send_rdy bit, which are equal to 1. All special registers are initialized to 0 upon reset, except for the IMR special register that must be initialized by the programmer. After reset-pin reset, receipt of an FRES symbol, or an open-link timeout, the Myrinet-link interface is held in the reset state until the ACTIVATE special register is written. While the Myrinet-link interface is in reset, all packets arriving from the network are dropped, but attempts to send packets from the LANai into the network are a programming error and produce undefined results. After the Myrinet-link interface is activated, the receive section will generate two tail flits (possibly preceded by one garbage data flit). These flits should be consumed by software. The Myrinet-link receive section begins to properly receive packets after it is activated and a GAP Myrinet- link control symbol is received (see Myrinet Link Specifications).