This is Info file inst.info, produced by Makeinfo-1.63 from the input file /ufs/lanai/LANai/L3.0_dox/inst.texinfo. This is a concise description of the LANai3 CPU core. The registers, instructions, and instruction pipeline are described here. Copyright (C) 1994, 1995 Myricom, Inc.  File: inst.info, Node: Top, Next: General, Prev: (dir), Up: (dir) The LANai3.0 Instruction Set **************************** $Revision: 1.22 $ * Menu: * General:: * Pipeline Operation:: Description of the operation of the LANai3 pipeline. * Dual-Context Operation:: Description of the LANai3's 2 contexts. * Registers:: Description of the LANai3 registers. * Instruction Set:: Detailed machine instruction details. * Instruction Interpretation:: When the actions specified by an instruction occur. * Debugging Support:: Hardware support for debugging. * Assembler:: * Concept Index:: Index of Concepts. -- The Detailed Node Listing -- The Machine Instruction Set * RI:: Register-Immediate. * RR:: Register-Register. * RRR:: Three-Register. * RM:: Register Memory. * RRM:: Register-Register-Memory. * BR:: Conditional-Branch. * PUNT:: Punt. * SLS:: Special Load Store. * SLI:: Special Load Immediate. * SPLS:: Special Partword Load Store. * SBR:: Special Branch (Experimental). Instruction Interpretation * Effects of nops:: `nop's can change the meaning of a program. * Modifying pc:: The LANai3 Assembler * General Assembler Info:: * Operands:: * Instruction Formats::  File: inst.info, Node: General, Next: Pipeline Operation, Prev: Top, Up: Top General Information ******************* *IMPORTANT: This document is ADVANCE INFORMATION, and is subject to change.* The LANai3 processor is a pipelined, RISC-style, load-store, 32-bit processor. Although an assembler exists, programmers are strongly encouraged to program this processor in C or C++, as the pipelined nature of this processor makes it difficult to write correct assembly code directly. In the remainder of this specification, we shall refer to 8-bit data units as bytes, to 16-bit units as half-words, and to 32-bit units as words. Pointers to successive words differ by 4, pointers to half-words differ by 2, and pointers to bytes differ by 1. All instructions are 1 word long. All word addresses must be word-aligned. All half-word addresses must be half-word aligned. Any least-significant bits of an address that would make a memory access non-aligned are ignored. Memory storage is big-endian.  File: inst.info, Node: Pipeline Operation, Next: Dual-Context Operation, Prev: General, Up: Top Pipeline Operation ****************** The LANai 3.0 processor is a 4-level-deep pipeline. An instruction that loads a register from a memory location, for example, can be depicted as follows: Time: 0 1 2 3 4 +------+ Iaddr: | 3044| (generate the instruction address) +------+------+ Fetch: | LOAD | (memory read to fetch the LOAD instruction) +------+------+ Compute: | ea | (compute the effective address) +------+------+ Memory: | read | (memory read to fetch the data) +------+ Only those instructions that access memory -- loads and stores -- use the 4th stage in the pipeline. If this `LOAD' instruction were followed by a Register-Immediate (RI) and then a Register-Register (RR) instruction, the pipelining of the execution of this instruction context could be depicted as follows: Time: 0 1 2 3 4 5 +------+------+------+ Iaddr: | 3044| 3048| 3052| +------+------+------+------+ Fetch: | LOAD | RI | RR | +------+------+------+------+ Compute: | ea | RI | RR | +------+------+------+ Memory: | read | +------+ The meaning of instructions is tied to the pipeline, and, in the remainder of this document, the instructions are defined operationally, in terms of the pipeline. In the example above, the `LOAD' instruction modifies its destination register (at least conceptually) at time 4. If this same register were a source in the Register-Immediate instruction, the source register contents for the RI instruction would be those after time 3, i.e., before the result of the memory read is placed into this register. Putting a null operation (`nop') between the `LOAD' and the RI instruction would change the meaning of the program. At each time step, up to two registers may be specified as the destination registers: one for the memory load, and the other for the regular computation. If these two destinations are the same register, the computed value is written, and the loaded value is discarded. Due to memory contention, some of the time steps may take more than one clock cycle (see the `LANai 3.0 specification' for memory-arbitration details). However, regardless of the number of wait-states that may be introduced, the processor state changes are guaranteed to follow the pipeline diagrams presented in this document.  File: inst.info, Node: Dual-Context Operation, Next: Registers, Prev: Pipeline Operation, Up: Top Dual-Context Operation ********************** An unusual feature of the LANai 3.0 processor is that it is a dual-context machine. The state of each context is contained in the CPU's general-purpose registers and five, programmer-accessible memory-mapped state registers: (`IPF', `CUR', `PREV', `DPF', `DATA'). One context is interruptable, and we shall refer to it as the "user" context. An interrupt during the execution of the user context causes the processor to switch to the other, "system", context. The system context is not interruptable. The system context transfers execution to the user context by executing the `punt' assembly instruction (*note PUNT::.). Executing the `punt' instruction in the user context similarly switches execution to the system context. Upon reset, the LANai processor begins executing code in the system context, starting from address 0. The interrupt handling is described in detail in the `LANai 3.0 specification'. The entire pipeline switches context at once, as illustrated in the following diagram. Unless the alternate context changes the original-context's state registers, the execution is guaranteed to follow the pipeline diagrams presented in this document. Time: 0 1 2 3 3 4 5 +------+------+------+ + Iaddr: | 3044| 3048| 3052| | +------+------+------+ +------+ Fetch: | LOAD | RI | operation | RR | +------+------+ of the other +------+------+ Compute: | ea | context | RI | RR | +------+ +------+------+ Memory: | | read | + +------+  File: inst.info, Node: Registers, Next: Instruction Set, Prev: Dual-Context Operation, Up: Top Registers ********* Registers are denoted as `r'I, where 0 <= i < 32. `r0'-`r4' and `r28'-`r31' are special registers: `r0' contains 0. `r0' may be the destination register of an instruction; if so, the result is discarded. `r1' contains 0xFFFFFFFF. `r1' may be the destination register of an instruction; if so, the result is discarded. `r2' is the program counter (`pc') of the current context: ----------------------------------------------------------------- | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |0.0| ----------------------------------------------------------------- word address Instructions that specify `pc' as the destination register modify `pc' in the same way and at the same time as any other register, but they also affect the execution flow. If not written by an instruction during a time-step, the program counter increments by four. The two low-order bits are hard-wired to zero. `r3' holds the program status word (`ps') of the current context, ----------------------------------------------------------------- |0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.U.C.V.N.Z| ----------------------------------------------------------------- which includes the Zero, Negative, oVerflow, and Carry flags of the current context in its least significant bits. The `U' field indicates the current context, 0 for system, 1 for user, and is hard-wired into `ps' of each context. `r4-r27' are general-purpose registers. When a context switch occurs, the order of these registers is reversed. For example, data stored to `r4' of context 0 may be read out of `r27' by context 1. This mechanism allows to compiler to use only registers %r4-%r15, obviating the need to save registers after a context switch because the two contexts use different registers, while simultaneously allowing the two contexts to share compiled code. More generally, this scheme can be used by the compiler to allocate a set of local registers per context, and a set of registers that are shared between the two contexts. `r28' is the process status word of the alternate (inactive) context (`aps'). `r29' is the program counter of the alternate (inactive) context (`apc'). `r30' is the interrupt mask register (`imr'). `r31' is the interrupt status register (`isr'). For additional interrupt-handling details, consult the `LANai 3.0 Specification'.  File: inst.info, Node: Instruction Set, Next: Instruction Interpretation, Prev: Registers, Up: Top The Machine Instruction Set *************************** *Note: All undefined bits in the instruction set (including those denoted by `-') are reserved and should be 0.* * Menu: * RI:: Register-Immediate. * RR:: Register-Register. * RRR:: Three-Register. * RM:: Register Memory. * RRM:: Register-Register-Memory. * BR:: Conditional-Branch. * PUNT:: Punt. * SLS:: Special Load Store. * SLI:: Special Load Immediate. * SPLS:: Special Partword Load Store. * SBR:: Special Branch (Experimental).  File: inst.info, Node: RI, Next: RR, Prev: Instruction Set, Up: Instruction Set Register Immediate (RI) ======================= Opcode: ----------------------------------------------------------------- |0.A.A.A| . . . . | . . . . |F.H| . . . . . . . . . . . . . . . | ----------------------------------------------------------------- opcode Rd Rs1 constant (16) Action: Rd <- Rs1 op constant Timing: Time: -1 0 1 2 +-----+ Iaddr: | | +-----+-----+ Fetch: | RI | +-----+-----+ Compute: | op | +-----+ `Rd' is (or appears to be) changed at time 2, and `Rs1' is its contents after time 1. Except for shift instructions, `H' determines whether the constant is in the high (1) or low (0) word. The other halfword is 0x0000, except for the `AND' instruction (`AAA' = 100), for which the other halfword is 0xFFFF, and shifts (`AAA' = 111), for which the constant is sign extended. `F' determines whether the instruction modifies (1) or does not modify (0) the program flags. `AAA' specifies the operation: `add' (000), `addc' (001), `sub' (010), `subb' (011), `and' (100), `or' (101), `xor' (110), or `shift' (111). For the shift, `H' specifies a logical (0) or arithmetic (1) shift. The amount and direction of the shift are determined by the sign extended constant interpretted as a two's complement number. The shift operation is defined only for the range of: 31 ... 0 -1 ... -31 \ / \ / left right shift shift If and only if the `F' bit is 1, RI instructions modify the condition bits, `Z' (Zero), `N' (Negative), `V' (oVerflow), and `C' (Carry), according to the result. If the flags are updated, they are updated as follows: `Z' is set if the result is zero and cleared otherwise. `N' is set to the most significant bit of the result. `V' For arithmetic instructions (`add', `addc', `sub', `subb') `V' is set if the sign (most significant) bits of the input operands are the same but different from the sign bit of the result and cleared otherwise. For other RI instructions, `V' is cleared. `C' For arithmetic instructions, `C' is set/cleared if there is/is not a carry generated out of the most significant when performing the twos-complement addition (`sub(a,b) == a + ~b + 1', `subb(a,b) == a + ~b + `C''). For left shifts, `C' is set to the least significant bit discarded by the shift operation. For all other operations, `C' is cleared. A Jump is accomplished by `Rd' being `pc', and it has one shadow. The all 0s word is the instruction `R0 <- R0 + 0', which is a no-op.  File: inst.info, Node: RR, Next: RRR, Prev: RI, Up: Instruction Set Register Register (RR) ====================== Opcode: ----------------------------------------------------------------- |1.1.0.0| . . . . | . . . . |F.-| . . . . |B.B.B|J.J.J.J.J|-.-.-| ----------------------------------------------------------------- opcode Rd Rs1 Rs2 \ operation / Action: `Rd <- Rs1 op Rs2' Timing: Time: -1 0 1 2 +-----+ Iaddr: | | +-----+-----+ Fetch: | RR | +-----+-----+ Compute: | op | +-----+ `Rd' is changed at time 2, and `Rs1' and `Rs2' are their values after time 1. `F' determines whether the instruction modifies (1) or does not modify (0) the program flags. `BBB' determines the operation: `add' (000), `addc' (001), `sub' (010), `subb' (011), `and' (100), `or' (101), `xor' (110), or "special" (111). The `JJJJJ' field is irrelevant except for special. `JJJJJ' determines which special operation is performed. `10---' is a logical shift, and `11---' is an arithmetic shift. The amount and direction of the shift are determined by the contents of `Rs2' interpretted as a two's complement number (in the same way as shifts in the Register-Immediate instructions in *Note RI::). All other `JJJJJ' combinations are reserved for instructions that may be defined in the future. If the `F' bit is 1, RR instructions modify the condition bits, `Z' (Zero), `N' (Negative), `V' (oVerflow), and `C' (Carry), according to the result. All RR instructions modify the `Z', `N', and `V' flags. Except for arithmetic instructions (`add', `addc', `sub', `subb'), `V' is cleared. Only arithmetic instructions and shifts modify `C'. Right shifts clear C. A Jump is accomplished by `Rd' being `pc', and it has one shadow.  File: inst.info, Node: RRR, Next: RM, Prev: RR, Up: Instruction Set Three-Register (RRR) ==================== Opcode: ----------------------------------------------------------------- |1.1.0.1| . . . . | . . . . |F.H| . . . . |A.A.A| . . . . |C.C.C| ----------------------------------------------------------------- opcode Rd Rs1 Rs2 op2 Rs3 op1 Action: Rd <- Rs1 op2 (Rs2 op1 Rs3) Timing: Time: -1 0 1 2 +-----+ Iaddr: | | +-----+-----+ Fetch: | RRR | +-----+-----+ Compute: |op op| +-----+ This instruction is similar to Register-Register (*note RR::.), except that the right operand is computed as (`Rs2 op1 Rs3') and `Rd' may not be 2 (`pc') or 31 (`isr'). It is performed in one time step. `Rd' is changed at time 2, and `Rs1', `Rs2', and `Rs3' are their values after time 1. `Rd' may not be 2 (`pc') or 31 (`isr'). `F' determines whether the instruction modifies (1) or does not modify (0) the program flags. `AAA' determines the second operation (`op2') in the same format as the RI instruction: `add' (000), `addc' (001), `sub' (010), `subb' (011), `and' (100), `or' (101), `xor' (110), or `shift' (111), and the result modifies the condition bits in the same way as the RI and RR instructions. For the shift, `H' determines a logical (0) or arithmetic (1) shift just as in the RI instruction, and the right operand determines the amount and direction of the shift in the same format as the RI and RR instructions. `CCC' determines the first operation (`op1'): `add' (000), `addc' (001), `sub' (010), `subb' (011), `and' (100), `or' (101), `xor' (110), or `sha' (arithmetic shift) (111). A Jump is accomplished by `Rd' being `pc', and it has one shadow.  File: inst.info, Node: RM, Next: RRM, Prev: RRR, Up: Instruction Set Register Memory (RM) ==================== Opcode: ----------------------------------------------------------------- |1.0.0.S| . . . . | . . . . |P.Q| . . . . . . . . . . . . . . . | ----------------------------------------------------------------- opcode Rd Rs1 constant (16) Action: Rd <- Memory(ea) (Load) see below for the Memory(ea) <- Rd (Store) definition of ea. Timing: Time: -1 0 1 2 3 +-----+ Iaddr: | | +-----+-----+ Fetch: | RM | +-----+-----+ Compute: | ea | (compute the effective address) +-----+-----+ Memory: | r/w | +-----+ `S' determines whether the instruction is a Load (0) or a Store (1). Depending on `S', `Rd' or Memory contents is changed at time 3, and `Rs1' is its value after time 1. If `Rs1' is changed, the change occurs at time 2. On a store, the value of `Rd' written to memory is the value after time 1. In other words, loads have a shadow, but stores do not. PQ operation -- ------------------------------------------ 00 ea = Rs1 01 ea = Rs1, Rs1 <- Rs1 + constant 10 ea = Rs1 + constant 11 ea = Rs1 + constant, Rs1 <- Rs1 + constant The constant is sign-extended for this instruction. `Rd' may not be 2 (`pc') or 31 (`isr'). A Jump is accomplished by `Rd' being `pc', and it has *two* shadows.  File: inst.info, Node: RRM, Next: BR, Prev: RM, Up: Instruction Set Register Register Memory (RRM) ============================== Opcode: ----------------------------------------------------------------- |1.0.1.S| . . . . | . . . . |P.Q| . . . . |B.B.B|J.J.J.J.J|Y.L.E| ----------------------------------------------------------------- opcode Rd Rs1 Rs2 \ operation / Action: Rd <- Memory(ea) (Load) see below for the Memory(ea) <- Rd (Store) definition of ea. Timing: Time: -1 0 1 2 3 +-----+ Iaddr: | | +-----+-----+ Fetch: | RRM | +-----+-----+ Compute: | ea | (compute the effective address) +-----+-----+ Memory: | r/w | +-----+ The RRM instruction is identical to the RM (*note RM::.) instruction (including the fact that `Rd' may not be 2 (`pc') or 31 (`isr')) except that 1. `Rs1 + constant' is replaced with `Rs1 op Rs2', where `op' is determined in the same way as in the RR instruction (*note RR::.) and 2. part-word memory accesses are allowed as specified below. If `BBB' != 111 (i.e.: For all but shift operations): If `YLE' = 01- => fuLl-word memory access If `YLE' = 00- => half-word memory access If `YLE' = 10- => bYte memory access If `YLE' = --1 => loads are zEro extended If `YLE' = --0 => loads are sign extended If `BBB' = 111 (For shift operations): fullword memory access are performed. All part-word loads write the least significant part of the destination register with the higher-order bits zero- or sign-extended. All part-word stores store the least significant part-word of the source register in the destination memory location. A Jump is accomplished by `Rd' being `pc', and it has *two* shadows.  File: inst.info, Node: BR, Next: PUNT, Prev: RRM, Up: Instruction Set Conditional Branch (BR) ======================= ----------------------------------------------------------------- |1.1.1.0|D.D.D| . . . . . . . . . . . . . . . . . . . . . . |R.I| ----------------------------------------------------------------- opcode condition constant (23) Action: `R' = 0: if (condition) { `pc' <- 4*(zero-extended constant) } `R' = 1: if (condition) { `pc' <- `pc' + 4*(sign-extended constant) } Timing: Time: -1 0 1 2 +-----+ Iaddr: | | +-----+-----+ Fetch: | BR | +-----+-----+ Compute: | add | +-----+ `R'=0 specifies an absolute branch and `R'=1 specifies a relative branch. The constant is scaled as shown by its position in the instruction word such that it specifies word-aligned addresses in the range [0,2^25-4] if `R'=0 or the range [-2^24,2^24-4] if `R' = 1. The condition after time 1 determines whether the `pc' is changed at time 2. For a relative branch that is taken, the value of `R2' after time 1 is added to the scaled and sign-extended constant. One instruction fetched after the BR is always executed before execution resumes at the location specified by the branch instruction. That is, the branch has one shadow. The `DDDI' field selects one of the following logical functions of the flags (the `I' (Invert sense) bit inverts the sense of the condition): DDDI logical function [code, used for...] ---- -------------------------------------- ------------------------ 0000 1 [T, true] 0001 0 [F, false] 0010 C AND Z' [HI, high] 0011 C' OR Z [LS, low or same] 0100 C' [CC, carry cleared] 0101 C [CS, carry set] 0110 Z' [NE, not equal] 0111 Z [EQ, equal] 1000 V' [VC, oVerflow cleared] 1001 V [VS, oVerflow set] 1010 N' [PL, plus] 1011 N [MI, minus] 1100 (N AND V) OR (N' AND V') [GE, greater than or equal] 1101 (N AND V') OR (N' AND V) [LT, less than] 1110 (N AND V AND Z') OR (N' AND V' AND Z') [GT, greater than] 1111 (Z) OR (N AND V') OR (N' AND V) [LE, less than or equal]  File: inst.info, Node: PUNT, Next: SLS, Prev: BR, Up: Instruction Set Punt (PUNT) =========== Opcode: ----------------------------------------------------------------- |1.1.1.1.-.-.-.-.-.-.-.-.-.-.1.1.1.1.1.1.1.1.1.1.-.1.-.-.-.1.1.1| ----------------------------------------------------------------- Action: Toggles the context. The timing is the same as for the RI (*note RI::.) instruction. The PUNT instruction switches execution to the alternate context. This instruction has no shadow. The context switch occurs as described in *Note Dual-Context Operation::, with the switch occuring after the PUNT instructions is actually executed (the "Compute" pipeline stage).  File: inst.info, Node: SLS, Next: SLI, Prev: PUNT, Up: Instruction Set Special Load/Store (SLS) ======================== Opcode: ----------------------------------------------------------------- |1.1.1.1| . . . . | . . . . |0.S| . . . . . . . . . . . . . . . | ----------------------------------------------------------------- opcode Rd addr 5msb's address 16 lsb's Action: If S = 0 (LOAD): Rd <- Memory(address); If S = 1 (STORE): Memory(address) <- Rd The timing is the same as for RM (*note RM::.) and RRM (*note RRM::.) instructions. The two low-order bits of the 21-bit address are ignored. The address is zero extended. Fullword memory accesses are performed. `Rd' may not be 2 (`pc') or 31 (`isr').  File: inst.info, Node: SLI, Next: SPLS, Prev: SLS, Up: Instruction Set Special Load Immediate (SLI) ============================ Opcode: ----------------------------------------------------------------- |1.1.1.1| . . . . | . . . . |1.0| . . . . . . . . . . . . . . . | ----------------------------------------------------------------- opcode Rd const 5msb's constant 16 lsb's Action: Rd <- constant The 21-bit constant is zero-extended. The timing is the same as the RM instruction (*note RM::.).  File: inst.info, Node: SPLS, Next: SBR, Prev: SLI, Up: Instruction Set Special Part-word Load/Store (SPLS) =================================== Opcode: ----------------------------------------------------------------- |1.1.1.1| . . . . | . . . . |1.1.0.Y.S.E.P.Q| . . . . . . . . . | ----------------------------------------------------------------- opcode Rd Rs1 constant Action: If `YS' = 11 (bYte Store): Memory(ea) <- (least significant byte of Rr) If `YS' = 01 (halfword Store): Memory(ea) <- (least significant half-word of Rr) If `YS' = 10 (bYte load): Rr <- Memory(ea) If `YS' = 00 (halfword load): Rr <- Memory(ea) [Note: here ea is determined as in the the RM instruction. ] If `SE' = 01 then the value is zEro extended before being loaded into Rd. If `SE' = 00 then the value is sign extended before being loaded into Rd. `P' and `Q' are used to determine `ea' as in the RM instruction. The constant is sign extended. The timing is the same as the RM and RRM instructions. *Note RM:: and *Note RRM::. `Rd' may not be 2 (`pc') or 31 (`isr'). All part-word loads write the part-word into the least significant part of the destination register, with the higher-order bits zero- or sign-extended. All part-word stores store the least significant part-word of the source register into the destination memory location.  File: inst.info, Node: SBR, Prev: SPLS, Up: Instruction Set Special Branch (SBR) ==================== Opcode: ----------------------------------------------------------------- |1.1.1.1|D.D.D|-.-| . . . . |1.1.1.1.0.0.0.0.0.0|-.-.-.-.-|0.0.I| ----------------------------------------------------------------- opcode Rs1 Rs3 Action: pc <-conditionally- Rs1 add Rs3 "`pc <-conditionally-'" means the `pc' is modified if and only if the condition specified by `DDDI' is satisfied, as in the BR instruction (*note BR::.). The timing is the same as in the BR instruction. *WARNING: The SBR instruction is experimental and may not be supported in future versions of the chip.*  File: inst.info, Node: Instruction Interpretation, Next: Debugging Support, Prev: Instruction Set, Up: Top Instruction Interpretation ************************** The instructions of the LANai 3.0 processor are defined in terms of the pipeline, and the processor does *not* attempt to preserve the sequential semantics of the source assembly program. No data or control hazards stall the pipeline, only denied memory accesses do. The unit of execution of the processor is the "time step", which takes as long as necessary for all four pipeline stages to complete, and, at least conceptually, all processor-state changes occur instantaneously, in between time steps. In absence of memory contention, each pipeline stage takes one clock cycle (see the `LANai 3.0 specification' for memory-arbitration details), except for `punt', which takes two clock cycles. A program can specify multiple values to be written to a single destination register during a timestep. Such conflicts are resolved as if the register updates occured in the following order, in between time steps: 1. The `pc' is incremented by 4. 2. The value, if any, loaded from memory is written to the destination register. 3. Any other destination register is updated. 4. The flags in `ps' register are updated, if specified by the instruction being executed. The order of activities within a time step is not defined. In particular, if during a time step two memory accesses are required (instruction and data), they can (and do) take place in any order. * Menu: * Effects of nops:: `nop's can change the meaning of a program. * Modifying pc::  File: inst.info, Node: Effects of nops, Next: Modifying pc, Prev: Instruction Interpretation, Up: Instruction Interpretation The Effects of `nop's ===================== The program: ld 0xC[%r8],%r7 ! R7 <- Memory( R8 + 0xC ) /* RM */ add %r7,%r9,%r8 ! R8 <- R7 + R9 /* RR */ is *not* equivalent to the program: ld 0xC[%r8],%r7 ! R7 <- Memory( R8 + 0xC ) /* RM */ nop ! R0 <- R0 + 0 /* a RI no-op */ add %r7,%r9,%r8 ! R8 <- R7 + R9 /* RR */ The meaning of the instructions is defined in terms of the pipeline. For the first program, the execution would be performed as follows: Time: 0 1 2 3 4 +-------+-------+ Iaddr: | 0| 4| +-------+-------+-------+ Fetch: | RM | RR | +-------+-------+-------+ Compute: | ea | RR | +-------+-------+ Memory: | r/w | +-------+ such that `R7' is modified by the RM instruction at time 4, and the `R7' referred to in the RR instruction is its contents before it is modified by the RM instruction. In the execution of the second program: Time: 0 1 2 3 4 +-------+-------+-------+ Iaddr: | 0| 4| 8| +-------+-------+-------+-------+ Fetch: | RM | nop | RR | +-------+-------+-------+-------+ Compute: | ea | nop | RR | +-------+-------+-------+ Memory: | r/w | +-------+ the `R7' referred to in the RR instruction is its contents after it is modified by the RM instruction.  File: inst.info, Node: Modifying pc, Prev: Effects of nops, Up: Instruction Interpretation Modifying `pc' (Program Counter) ================================ Incrementing of the current `pc' is an implicit operation that fetches the value of the `pc' at the beginning of a time step and modifies the `pc' at the end of the time step. Programs that explicitly modify the `pc' override this implicit operation. In either case, the value of the `pc' at the *end* of a time step is used to fetch the instruction during the following time step. For example, the following program executes the shadow and then jumps to address 304: 0: bt 304 ! pc <- 304 /* BR */ 4: mov %r25,%r24 ! R24 <- R25 /* RR */ /* the shadow */ The behavior of the preceeding code is depicted in the following diagram: pc written here ... ... and that written value of pc | | is used to fetch the NEW v v instruction here. +-------+-------+-------+-------+ pc: |X 0|0 4|4 304|304 308| ... +-------+-------+-------+-------+ Iaddr: | 0| 4| 304| 308| ... +-------+-------+-------+-------+-------+ Fetch: | BR | RR | NEW | ... | +-------+-------+-------+-------+-------+ Compute: | BR | RR | ... | ... | +-------+-------+-------+-------+ In another example, the program 0: ld [28],%pc ! /*RM*/ pc <- Memory(28) /*here Memory(28) = 304*/ 4: mov %pc,%r27 ! /*RR*/ r27 <- pc /*these instructions...*/ 8: add %r26,3,%r26 ! /*RI*/ R26 <- R26 + 3 /*...will be executed. */ executes the two shadows and then jumps to address 304: pc is written here... ... and that value of pc | | is used to fetch an V V instruction here. +-------+-------+-------+-------+-------+ pc: |X 0|0 4|4 8|8 304|304 308| ... +-------+-------+-------+-------+-------+ Iaddr: | 0| 4| 8| 304| 308| ... +-------+-------+-------+-------+-------+-------+ Fetch: | RM | RR | RI | NEW | ... | ... +-------+-------+-------+-------+-------+-------+ Compute: | ea | RR | RI | ... | ... | +-------+-------+-------+-------+-------+ Memory: | read | +-------+ Although this processor does not directly support conditional branches to addresses greater than (2^25)-4, conditional branches to any memory location can be effected by taking the advantage of the property that memory loads into registers are overridden if they conflict with other writes to the same register. For example, the following relocatable code conditionally jumps to the address in memory location 304 if the `C' flag in the `%ps' register is clear by loading the address into the `pc' and then conditionally overriding the load with a branch instruction: 0: ld [304],%pc ! /*RM*/ pc <- Memory(304) 4: bcs.r 4 ! /*BR*/ pc <-conditionally- pc + 4 8: nop ! /*RI*/ does nothing  File: inst.info, Node: Debugging Support, Next: Assembler, Prev: Instruction Interpretation, Up: Top Debugging Support ***************** The debugging support of the LANai 3.0 processor enables debugging of programs that run in the user context. As discussed in the `LANai 3.0 specification', the `isr' register includes the `dbg_bit', which is always set to 1. As long as the corresponding bit in the `imr' register is set to 1, the interrupt request for the LANai 3.0 processor will be asserted. The following technique can be used for debugging code in the user context on a timestep-by-timestep basis: 1. The debugger, running in the non-interruptable, system context, sets the `dbg_bit' of `imr' to 1. 2. The debugger executes `punt' instruction, switching to user context. 3. The user executes for exactly one time-step (regardless of how many clock cycles it may take). 4. Because the user context is interruptable, the execution switches back to the system context.  File: inst.info, Node: Assembler, Next: Concept Index, Prev: Debugging Support, Up: Top The LANai3 Assembler ******************** * Menu: * General Assembler Info:: * Operands:: * Instruction Formats::  File: inst.info, Node: General Assembler Info, Next: Operands, Prev: Assembler, Up: Assembler General Assembler Info ====================== The LANai3 assember is `gas', the Gnu assembler from the Free Software Foundation. For most details about the assembler, see the `gas' documentation which comes with the assembler in the following formats: Gnu `info', Adobe PostScript, and plain text. The `gas' documentation is also available via the world wide web at `http://www.ns.utk.edu/gnu/gnu.html' Registers 0 to 31 are referred to, respectively, as `%r0' to `%r31'. Other recognized names are `%ps' (`%r3'), `%sp' (`%r4'), `%fp' (`%r5'), `%rv' (`%r8'), `%rca' (`%r15'), `%aps' (`%r28'), `%apc' (`%r29'), `%imr' (`%r30'), and `%isr' (`%r31'). They stand for, respectively, "`p'rocess `s'tatus word," "`s'tack `p'ointer," "`f'rame `p'ointer," "`r'return `v'alue," "`r'egister for `c'onstant `a'ddresses," "`a'lternate `p'rocess `s'tatus word," "`a'lternate `p'rogram `c'ounter," "`i'nterrupt `s'tatus `r'egister," and "`i'nterrupt `m'ask `r'egister." To prevent label-name-space polution, labels generated by the C compiler start with ``_'' if they correspond to a user variable or ``L'' if they correspond to a compiler-generated label. *The LANai3 is a pipelined processor.* Assembly programmers should understand the material in the sections *Note Pipeline Operation::, *Note Registers::, and *Note Instruction Interpretation:: before attempting to program this processor. Instructions modify the flags in the `ps' register under the following circumstances: 1. `ps' is explicitly named in an instruction as a destination register. 2. Flag updates are specified by the presence of ``.f'' in the instruction. If both (1) and (2) hold for an instruction, the updates occur sequentially: First the destination value is written to `ps', and then the flag values in `ps' are updated to reflect the value written to `ps'.  File: inst.info, Node: Operands, Next: Instruction Formats, Prev: General Assembler Info, Up: Assembler Operand Types ============= The following operand types may appear in assembly instructions: BRABS An unsigned, 23-bit, immediate absolute branch address or a register. Note that the 2 lsb's must be 0. BROFF A signed, 23-bit, immediate relative branch offset or a register. Note that the 2 lsb's must be 0. AND_CONST A 32 bit unsigned constant with either the high or low halfword == 0xffff CONST A 32 bit unsigned constant with either the high or low halfword == 0 LCONST A 21 bit unsinged constant SIGNED_CONST_10 A 10 bit signed constant SIGNED_CONST A 16 bit signed constant SHIFT_CONST A 6 bit signed constant in the range [-31,31] OP1 One of "`add', `addc', `sub', `subc', `and', `or', `xor', `sha'" OP2 One of "`add', `addc', `sub', `subc', `and', `or', `xor', `sh', `sha'" RDEST A register RDEST_LD A register other than 2 (`pc') or 31 (`isr'). RDEST_PUT A register other than 2 (`pc') or 31 (`isr'). SRC1 A register SRC2 A register SRC3 A register Negative constants may be written with a `-' sign or as a 32-bit constant, which will be truncated appropriately. For example, `-4' and `0xFFFFFFFC' are valid SHIFT_CONSTs.  File: inst.info, Node: Instruction Formats, Prev: Operands, Up: Assembler Instruction Formats =================== In this section: * Braces (`<>') indicate optional text. E.g.: "cat" matches "cat" or "concat" only. * A vertical bar ("|") indicates a list of alternative matches. E.g.: "walk" matches "walk", "walks", "walking", or "walked"<. * Braces (`{}') indicate mandatory text. E.g.: "walk{s|ing|ed}" matches "walks", "walking", or "walked" only. * For all instructions, unless otherwise specified, `pc' <- `pc' + 4 . Instruction Machine Instruction ------------------------------------------------------------------- add<.f> SRC1, CONST, RDEST RI RDEST <- SRC1 + CONST NOTES: (1),(4) add<.f> SRC1, SRC2, RDEST RR RDEST <- SRC1 + SRC2 NOTES: (1),(4) addc<.f> SRC1, SRC2, RDEST RI RDEST <- SRC1 + SRC2 + C NOTES: (1),(4) C is the carry flag from %ps addc<.f> SRC1, CONST, RDEST RR RDEST <- SRC1 + CONST + C NOTES: (1),(4) C is the carry flag from %ps and<.f> SRC1, AND_CONST, RDEST RI RDEST <- SRC1 & AND_CONST NOTES: (1),(4) and<.f> SRC1, SRC2, RDEST RR RDEST <- SRC1 & SRC2 NOTES: (1),(4) b?? BRABS BR if ( ?? condition is true ) then %pc <- BRABS NOTES: (6) b?? SRC3 SBR if ( ?? condition is true ) then %pc <- SRC3 NOTES: (6) b??.r BROFF BR if (?? condition is true) then %pc <- %pc + BROFF NOTES: (5), (6) b?? SRC1 add SRC3 SBR if (?? condition is true) then %pc <- SRC1 + SRC2 NOTES: (6), (7) In the ``b??'' instructions above, ``b??'' must be replaced with one of the branch mnemonics in the table below. Each of these branch mnemonics specifies the conditions under which the branch is taken. *Note BR:: inst. branch condition branches if true ----- ---------------- ---------------- bt true 1 bf false 0 bhi|bugt high C AND Z' bls|bule low or same C' OR Z bcc|bult carry clear C' bcs|buge carry set C bne not equal Z' beq equal Z bvc overflow cleared V' bvs overflow set V bpl plus N' bmi minus N bge greater than or equal (N AND V) OR (N' AND V') blt less than (N AND V') OR (N' AND V) bgt greater than (N AND V AND Z') OR (N' AND V' AND Z') Instruction Machine Instruction ------------------------------------------------------------------- ld SIGNED_CONST[SRC1], RDEST_LD RM RDEST_LD <- mem(SRC1+SIGNED_CONST) NOTES: (2), (3) ld SRC2[SRC1], RDEST_LD RRM RDEST_LD <- mem(SRC1+SRC2) NOTES: (2),(3) ld{.h|.b} SIGNED_CONST_10[SRC1], RDEST_LD SPLS RDEST_LD <- mem(SRC1+SIGNED_CONST_10) NOTES: (2),(3) ld SIGNED_CONST[*SRC1], RDEST_LD RM RDEST_LD <- mem(SRC1+SIGNED_CONST) SRC1 <- SRC1+SIGNED_CONST NOTES: (2),(3) ld [{--|++}SRC1], RDEST_LD RM RDEST_LD <- mem(SRC1 {-|+} 4) SRC1 <- SRC1 {-|+} 4 NOTES: (2),(3) ld.h [{--|++}SRC1], RDEST_LD SPLS RDEST_LD <- mem(SRC1 {-|+} 2) SRC1 <- SRC1 {-|+} 2 NOTES: (2),(3) ld.b [{--|++}SRC1], RDEST_LD SPLS RDEST_LD <- mem(SRC1 {-|+} 1) SRC1 <- SRC1 {-|+} 1 NOTES: (2),(3) ld SRC2[*SRC1], RDEST_LD RRM RDEST_LD <- mem(SRC1+SRC2) SRC1 <- SRC1+SRC2 NOTES: (2),(3) ld{.h|.b} SIGNED_CONST_10[*SRC1], RDEST_LD SPLS RDEST_LD <- mem(SRC1+SIGNED_CONST_10) SRC1 <- SRC1+SIGNED_CONST_10 NOTES: (2),(3) ld SIGNED_CONST[SRC1*], RDEST_LD RM RDEST_LD <- mem(SRC1) SRC1 <- SRC1+SIGNED_CONST NOTES: (2),(3) ld [SRC1{--|++}], RDEST_LD RM RDEST_LD <- mem(SRC1) SRC1 <- SRC1 {-|+} 4 NOTES: (2),(3) ld.h [SRC1{--|++}], RDEST_LD SPLS RDEST_LD <- mem(SRC1) SRC1 <- SRC1 {-|+} 2 NOTES: (2),(3) ld.b [SRC1{--|++}], RDEST_LD SPLS RDEST_LD <- mem(SRC1) SRC1 <- SRC1 {-|+} 1 NOTES: (2),(3) ld SRC2[SRC1*], RDEST_LD RRM RDEST_LD <- mem(SRC1) SRC1 <- SRC1+SRC2 NOTES: (2),(3) ld{.h|.b} SIGNED_CONST_10[SRC1*], RDEST_LD SPLS RDEST_LD <- mem(SRC1) SRC1 <- SRC1+SIGNED_CONST_10 NOTES: (2),(3) ld [SRC1 OP2 SRC2], RDEST_LD RRM RDEST_LD <- mem(SRC1 OP2 SRC2) NOTES: (2),(3) ld [*SRC1 OP2 SRC2], RDEST_LD RRM RDEST_LD <- mem(SRC1 OP2 SRC2) SRC1 <- SRC1 OP2 SRC2 NOTES: (2),(3) ld [SRC1* OP2 SRC2], RDEST_LD RRM RDEST_LD <- mem(SRC1) SRC1 <- SRC1 OP2 SRC2 NOTES: (2),(3) ld [LCONST], RDEST_LD SLS RDEST <- mem(LCONST) NOTES: (2),(3) Instruction Machine Instruction ------------------------------------------------------------------- mov CONST,SRC1 RI SRC1 <- CONST NOTES: (1) mov SRC2,SRC1 RR SRC1 <- SRC2 NOTES: (1) mov LCONST,SRC1 SLI SRC1 <- LCONST NOTES: (1) mov AND_CONST,SRC1 RI SRC1 <- AND_CONST NOTES: (1) nop RI (does nothing) or<.f> SRC1, CONST, RDEST RI RDEST <- SRC1 | SRC2 NOTES: (1),(4) or<.f> SRC1, SRC2, RDEST RR RDEST <- SRC1 | SRC2 NOTES: (1),(4) put SRC1 OP2<.F> ( SRC2 OP1 SRC3 ), RDEST_PUT RRR RDEST <- SRC1 OP2 ( SRC2 OP1 SRC3 ) NOTES: (1) * Flags set by result of op2 sh<.f> SRC1, SHIFT_CONST, RDEST RI RDEST <- SRC1 << SHIFT_CONST NOTES: (1),(4), (7) logical shift performed sh<.f> SRC1, SRC2, RDEST RR IF(31>=SRC2>=0)THEN RDEST <- SRC1 << SHIFT_CONST ELSE IF(0>SRC2>=-31) RDEST <- SRC1 >> -SHIFT_CONST ELSE result undefined NOTES: (1),(4), logical shift performed sha<.f> SRC1, SHIFT_CONST, RDEST RI RDEST <- SRC1 << SHIFT_CONST NOTES: (1),(4), (7) arithmetic shift performed sha<.f> SRC1, SRC2, RDEST RR IF(31>=SRC2>=0)THEN RDEST <- SRC1 << SHIFT_CONST ELSE IF(0>SRC2>=-31) RDEST <- SRC1 >> -SHIFT_CONST ELSE result is undefined NOTES: (1),(4) Instruction Machine Instruction ------------------------------------------------------------------- st SRC1, SIGNED_CONST[SRC3] RM mem(SRC3+SIGNED_CONST) <- SRC1 NOTES: (3) st{.h|.b} SRC1, SIGNED_CONST_10[SRC3] SPLS mem(SRC3+SIGNED_CONST_10) <- SRC1 NOTES: (3) st<.h|.b> SRC1, SRC2[SRC3] RRM mem(SRC3+SRC2) <- SRC1 NOTES: (3) st SRC1, SIGNED_CONST[*SRC3] RM mem(SRC3+SIGNED_CONST) <- SRC1 SRC3 <- SRC3+SIGNED_CONST NOTES: (3) st{.h|.b} SRC1, SIGNED_CONST_10[*SRC3] SPLS mem(SRC3+SIGNED_CONST_10) <- SRC1 SRC3 <- SRC3+SIGNED_CONST_10 NOTES: (3) st SRC1, [{--|++}SRC3] RM mem(SRC3 {-|+} 4) <- SRC1 SRC3 <- SRC3 {-|+} 4 NOTES: (3) st.h SRC1, [{--|++}SRC3] SPLS mem(SRC3 {-|+} 2) <- SRC1 SRC3 <- SRC3 {-|+} 2 NOTES: (3) st.b SRC1, [{--|++}SRC3] SPLS mem(SRC3 {-|+} 1) <- SRC1 SRC3 <- SRC3 {-|+} 1 NOTES: (3) st<.h|.b> SRC1, SRC2[*SRC3] RRM mem(SRC3+SRC2) <- SRC1 SRC3 <- SRC3+SRC2 NOTES: (3) st SRC1, SIGNED_CONST[SRC3*] RM mem(SRC3) <- SRC1 SRC3 <- SRC3+SIGNED_CONST NOTES: (3) st{.h|.b} SRC1, SIGNED_CONST[SRC3*] SPLS mem(SRC3) <- SRC1 SRC3 <- SRC3+SIGNED_CONST NOTES: (3) st SRC1, [SRC3{--|++}] RM mem(SRC3) <- SRC1 SRC3 <- SRC3 {-|+} 4 NOTES: (3) st.h SRC1, [SRC3{--|++}] SPLS mem(SRC3) <- SRC1 SRC3 <- SRC3 {-|+} 2 NOTES: (3) st.b SRC1, [SRC3{--|++}] SPLS mem(SRC3) <- SRC1 SRC3 <- SRC3 {-|+} 1 NOTES: (3) st<.h|.b> SRC1, SRC2[SRC3*] RRM mem(SRC3) <- SRC1 SRC3 <- SRC3+SRC2 NOTES: (3) st<.h|.b> RDEST, [SRC1 OP2 SRC2] RRM mem(SRC1 OP2 SRC2) <- RDEST st<.h|.b> RDEST, [*SRC1 OP1 SRC2] RRM mem(SRC1 OP1 SRC2) <- RDEST src1 <- src1 op2 src2 st<.h|.b> RDEST, [SRC1* OP2 SRC2] RRM mem(SRC1) <- RDEST src1 <- src1 op2 src2 st RDEST, [LCONST] SLS mem(LCONST) <- RDEST Instruction Machine Instruction ------------------------------------------------------------------- sub<.f> SRC1, CONST, RDEST RI RDEST <- SRC1 - CONST NOTES: (1),(4) sub<.f> SRC1, SRC2, RDEST RR RDEST <- SRC1 - SRC2 NOTES: (1),(4) subb<.f> SRC1, CONST, RDEST RI RDEST <- SRC1 - CONST + C NOTES: (1),(4) C is the carry bit from %ps subb<.f> SRC1, SRC2, RDEST RR RDEST <- SRC1 - SRC2 + C NOTES: (1),(4) C is the carry bit from %ps xor<.f> SRC1, CONST, RDEST RI RDEST <- SRC1 XOR CONST NOTES: (1),(4) xor<.f> SRC1, SRC2, RDEST RR RDEST <- SRC1 XOR SRC2 NOTES: (1),(4) Notes ----- 1. If the destination register is `pc', one more instruction will be executed before execution continues at the location specified by the addresse store to `pc' by this instruction. 2. a. Memory loads into `pc' have *two* shadows. That is, two more instructions will be executed after the instruction performing the load before execution resumes at the location specified by the value loaded into `pc'. b. The byte loaded by a `ld.b' or the halfword loaded by a `ld.h' instruction is sign-extended to 32 bits before being saved in RDEST. The byte loaded by a `uld.b' or the halfword loaded by a `uld.h' instruction is zero-extended to 32 bits before being saved in RDEST. c. RDEST in a `ld' instruction is not changed until after the following instruction. For further information, see *Note RM::. 3. `.h' => halfword memory access `.b' => byte memory access 4. `.f' => modify the flags 5. For more details about the timing of relative branch instructions, see *Note Modifying pc::. Relative branches branch relative to the current `pc'. The current `pc' contains the address of the *next* instruction to be executed. This is *usually* 4 greater than the address of the current instruction unless (a) the previous instruction was a branch, (b) the previous instruction was an ALU operation with `pc' as its destination register, or (c) the instruction *before* the previous instruction was any variant of `ld' with RDEST == `pc'. 6. Branches have a shadow. For futher information, see *Note BR:: and *Note Modifying pc::. 7. Here, a right shift is performed if SHIFT_CONST is negative.  File: inst.info, Node: Concept Index, Prev: Assembler, Up: Top Concept Index ************* * Menu: * %apc: General Assembler Info. * %aps: General Assembler Info. * %fp: General Assembler Info. * %imr: General Assembler Info. * %isr: General Assembler Info. * %ps: General Assembler Info. * %r0: General Assembler Info. * %r31: General Assembler Info. * %rca: General Assembler Info. * %rv: General Assembler Info. * %sp: General Assembler Info. * .f: General Assembler Info. * add.f instruction: Instruction Formats. * addc.f instruction: Instruction Formats. * addc instruction: Instruction Formats. * add instruction: Instruction Formats. * and.f instruction: Instruction Formats. * and instruction: Instruction Formats. * b??.r instructions: Instruction Formats. * b?? instructions: Instruction Formats. * bcc instruction: Instruction Formats. * bcs instruction: Instruction Formats. * beq instruction: Instruction Formats. * bf instruction: Instruction Formats. * bge instruction: Instruction Formats. * bgt instruction: Instruction Formats. * bhi instruction: Instruction Formats. * ble instruction: Instruction Formats. * bls instruction: Instruction Formats. * blt instruction: Instruction Formats. * bmi instruction: Instruction Formats. * bne instruction: Instruction Formats. * bpl instruction: Instruction Formats. * bt instruction: Instruction Formats. * buge instruction: Instruction Formats. * bugt instruction: Instruction Formats. * bule instruction: Instruction Formats. * bult instruction: Instruction Formats. * bvc instruction: Instruction Formats. * bvs instruction: Instruction Formats. * ld.b instruction: Instruction Formats. * ld.h instruction: Instruction Formats. * ld instruction: Instruction Formats. * mov instruction: Instruction Formats. * nop instruction: Instruction Formats. * nops, the effects of: Effects of nops. * or.f instruction: Instruction Formats. * or instruction: Instruction Formats. * pc, modifying: Modifying pc. * put: General Assembler Info. * sh.f instruction: Instruction Formats. * sha.f instruction: Instruction Formats. * sha instruction: Instruction Formats. * sh instruction: Instruction Formats. * st.b instruction: Instruction Formats. * st.h instruction: Instruction Formats. * st instruction: Instruction Formats. * sub.f instruction: Instruction Formats. * subb.f instruction: Instruction Formats. * subb (subtract with borrow instruction): Instruction Formats. * sub (subtract instruction): Instruction Formats. * uld.b instruction: Instruction Formats. * uld.h instruction: Instruction Formats. * uld instruction: Instruction Formats. * xor.f instruction: Instruction Formats. * xor (exclusive-or instruction): Instruction Formats. * gas: General Assembler Info. * _ in labels: General Assembler Info. * L in labels: General Assembler Info. * AND_CONST: Operands. * BRABS: Operands. * BROFF: Operands. * CONST: Operands. * LCONST: Operands. * OP1: Operands. * OP2: Operands. * RDEST_LD: Operands. * RDEST_PUT: Operands. * RDEST: Operands. * SHIFT_CONST: Operands. * SIGNED_CONST_10: Operands. * SRC1: Operands. * SRC2: Operands. * SRC3: Operands. * Adobe PostScript: General Assembler Info. * aligned: General. * arithmetic shift instruction: Instruction Formats. * Assembler, General Info: General Assembler Info. * assembly: General. * Big-Endian: General. * branch instructions: Instruction Formats. * byte: General. * byte load instruction: Instruction Formats. * byte load instruction, unsigned: Instruction Formats. * byte store instruction: Instruction Formats. * C: General. * C++: General. * carry clear, branch if: Instruction Formats. * carry set, branch if: Instruction Formats. * Conditional Branch (BR): BR. * Debugging Support: Debugging Support. * documentation: General Assembler Info. * Dual-Context Operation: Dual-Context Operation. * Effects of nops: Effects of nops. * equal, branch if: Instruction Formats. * exclusive-or instruction: Instruction Formats. * false, branch if: Instruction Formats. * flags: General Assembler Info. * Formats, instruction: Instruction Formats. * Free Software Foundation: General Assembler Info. * General Assembler Info: General Assembler Info. * greater than or equal, branch if: Instruction Formats. * greater than or equal, unsigned, branch if: Instruction Formats. * greater than, branch if: Instruction Formats. * half-word load instruction, unsigned: Instruction Formats. * half-word store instruction: Instruction Formats. * halfword: General. * halfword load instruction: Instruction Formats. * high or same, branch if: Instruction Formats. * info: General Assembler Info. * Info, General Assembler: General Assembler Info. * Instruction formats: Instruction Formats. * Instruction Interpretation: Instruction Interpretation. * Instruction Set, Machine: Instruction Set. * Labels, register: General Assembler Info. * less than or equal, branch if: Instruction Formats. * less than or equal, unsigned: Instruction Formats. * less than, branch if: Instruction Formats. * less than, unsigned, branch if: Instruction Formats. * load instruction: Instruction Formats. * load instruction, unsigned: Instruction Formats. * low or same, branch if: Instruction Formats. * Machine Instruction Set: Instruction Set. * minus, branch if: Instruction Formats. * Modifying pc: Modifying pc. * negative, branch if: Instruction Formats. * not equal, branch if: Instruction Formats. * op2: General Assembler Info. * Opcodes: Assembler. * Operand types: Operands. * overflow clear, branch if: Instruction Formats. * overflow set, branch if: Instruction Formats. * Pipeline: Pipeline Operation. * pipelined processor: General Assembler Info. * plain text: General Assembler Info. * plus, branch if: Instruction Formats. * positive, branch if: Instruction Formats. * PostScript: General Assembler Info. * processor, pipelined: General Assembler Info. * Punt (PUNT): PUNT. * Register Immediate (RI): RI. * Register Memory (RM): RM. * Register Register Memory (RRM): RRM. * Registers <1>: Registers. * Registers: General Assembler Info. * Registers labels: General Assembler Info. * shift instruction: Instruction Formats. * Special Branch (SBR): SBR. * Special Load Immediate (SLI): SLI. * Special Load/Store (SLS): SLS. * Special Part-word Load/Store (SPLS): SPLS. * store instruction: Instruction Formats. * Three-Register (RRR): RRR. * true, branch if: Instruction Formats. * unsigned greater than or equal, branch if: Instruction Formats. * unsigned less than or equal, branch if: Instruction Formats. * unsigned less than, branch if: Instruction Formats. * unsigned load instruction: Instruction Formats. * word: General. * World Wide Web: General Assembler Info. * WWW: General Assembler Info.  Tag Table: Node: Top292 Node: General1953 Node: Pipeline Operation2973 Node: Dual-Context Operation5889 Node: Registers7877 Node: Instruction Set10634 Node: RI11501 Node: RR14440 Node: RRR16496 Node: RM18513 Node: RRM20279 Node: BR22387 Node: PUNT25353 Node: SLS26081 Node: SLI26890 Node: SPLS27469 Node: SBR29043 Node: Instruction Interpretation29822 Node: Effects of nops31522 Node: Modifying pc33439 Node: Debugging Support36964 Node: Assembler37985 Node: General Assembler Info38197 Node: Operands40161 Node: Instruction Formats41530 Node: Concept Index55370  End Tag Table