IMPORTANT: This document is ADVANCE INFORMATION, and is subject to change.
The LANai3 processor is a pipelined, RISC-style, load-store, 32-bit processor.
Although an assembler exists, programmers are strongly encouraged to program this processor in C or C++, as the pipelined nature of this processor makes it difficult to write correct assembly code directly.
In the remainder of this specification, we shall refer to 8-bit data units as bytes, to 16-bit units as half-words, and to 32-bit units as words. Pointers to successive words differ by 4, pointers to half-words differ by 2, and pointers to bytes differ by 1. All instructions are 1 word long. All word addresses must be word-aligned. All half-word addresses must be half-word aligned. Any least-significant bits of an address that would make a memory access non-aligned are ignored. Memory storage is big-endian.