The LANai 3.0 processor is a 4-level-deep pipeline. An instruction that loads a register from a memory location, for example, can be depicted as follows:
Time: 0 1 2 3 4
+------+
Iaddr: | 3044| (generate the instruction address)
+------+------+
Fetch: | LOAD | (memory read to fetch the LOAD instruction)
+------+------+
Compute: | ea | (compute the effective address)
+------+------+
Memory: | read | (memory read to fetch the data)
+------+
Only those instructions that access memory -- loads and stores -- use the 4th stage in the pipeline.
If this LOAD instruction were followed by a Register-Immediate
(RI) and then a Register-Register (RR) instruction, the pipelining of
the execution of this instruction context could be depicted as follows:
Time: 0 1 2 3 4 5
+------+------+------+
Iaddr: | 3044| 3048| 3052|
+------+------+------+------+
Fetch: | LOAD | RI | RR |
+------+------+------+------+
Compute: | ea | RI | RR |
+------+------+------+
Memory: | read |
+------+
The meaning of instructions is tied to the pipeline, and, in the
remainder of this document, the instructions are defined operationally,
in terms of the pipeline. In the example above, the LOAD
instruction modifies its destination register (at least conceptually) at
time 4. If this same register were a source in the Register-Immediate
instruction, the source register contents for the RI instruction would
be those after time 3, i.e., before the result of the memory read is
placed into this register. Putting a null operation (nop)
between the LOAD and the RI instruction would change the meaning
of the program.
At each time step, up to two registers may be specified as the destination registers: one for the memory load, and the other for the regular computation. If these two destinations are the same register, the computed value is written, and the loaded value is discarded.
Due to memory contention, some of the time steps may take more than one clock cycle (see the LANai 3.0 specification for memory-arbitration details). However, regardless of the number of wait-states that may be introduced, the processor state changes are guaranteed to follow the pipeline diagrams presented in this document.