Registers

Registers are denoted as ri, where 0 <= i < 32.

r0-r4 and r28-r31 are special registers:

r0

contains 0. r0 may be the destination register of an instruction; if so, the result is discarded.

r1

contains 0xFFFFFFFF. r1 may be the destination register of an instruction; if so, the result is discarded.

r2

is the program counter (pc) of the current context:

-----------------------------------------------------------------
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |0.0|
-----------------------------------------------------------------
                                    word address 

Instructions that specify pc as the destination register modify pc in the same way and at the same time as any other register, but they also affect the execution flow. If not written by an instruction during a time-step, the program counter increments by four. The two low-order bits are hard-wired to zero.

r3

holds the program status word (ps) of the current context,

-----------------------------------------------------------------
|0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.U.C.V.N.Z|
-----------------------------------------------------------------

which includes the Zero, Negative, oVerflow, and Carry flags of the current context in its least significant bits. The `U' field indicates the current context, 0 for system, 1 for user, and is hard-wired into ps of each context.

r4-r27

are general-purpose registers. When a context switch occurs, the order of these registers is reversed. For example, data stored to r4 of context 0 may be read out of r27 by context 1. This mechanism allows to compiler to use only registers %r4-%r15, obviating the need to save registers after a context switch because the two contexts use different registers, while simultaneously allowing the two contexts to share compiled code. More generally, this scheme can be used by the compiler to allocate a set of local registers per context, and a set of registers that are shared between the two contexts.

r28

is the process status word of the alternate (inactive) context (aps).

r29

is the program counter of the alternate (inactive) context (apc).

r30

is the interrupt mask register (imr).

r31

is the interrupt status register (isr). For additional interrupt-handling details, consult the LANai 3.0 Specification.