Note: All undefined bits in the instruction set (including those denoted by `-') are reserved and should be 0.
----------------------------------------------------------------- |0.A.A.A| . . . . | . . . . |F.H| . . . . . . . . . . . . . . . | ----------------------------------------------------------------- opcode Rd Rs1 constant (16)
Rd <- Rs1 op constant
Time: -1 0 1 2
+-----+
Iaddr: | |
+-----+-----+
Fetch: | RI |
+-----+-----+
Compute: | op |
+-----+
Rd is (or appears to be) changed at time 2, and Rs1 is its
contents after time 1.
Except for shift instructions, `H' determines whether the constant
is in the high (1) or low (0) word. The other halfword is 0x0000,
except for the AND instruction (`AAA' = 100), for which the
other halfword is 0xFFFF, and shifts (`AAA' = 111), for which the
constant is sign extended.
`F' determines whether the instruction modifies (1) or does not modify (0) the program flags.
`AAA' specifies the operation: add (000), addc (001),
sub (010), subb (011), and (100), or (101),
xor (110), or shift (111). For the shift, `H' specifies a
logical (0) or arithmetic (1) shift. The amount and direction of the
shift are determined by the sign extended constant interpretted as a
two's complement number. The shift operation is defined only for the
range of:
31 ... 0 -1 ... -31 \ / \ / left right shift shift
If and only if the `F' bit is 1, RI instructions modify the condition bits, `Z' (Zero), `N' (Negative), `V' (oVerflow), and `C' (Carry), according to the result. If the flags are updated, they are updated as follows:
add, addc, sub,
subb) `V' is set if the sign (most significant) bits of the
input operands are the same but different from the sign bit of the
result and cleared otherwise. For other RI instructions, `V' is
cleared.
sub(a,b) == a + ~b + 1,
subb(a,b) == a + ~b + `C'). For left shifts,
`C' is set to the least significant bit discarded by the shift
operation. For all other operations, `C' is cleared.
A Jump is accomplished by Rd being pc, and it has one shadow.
The all 0s word is the instruction R0 <- R0 + 0, which is a no-op.
----------------------------------------------------------------- |1.1.0.0| . . . . | . . . . |F.-| . . . . |B.B.B|J.J.J.J.J|-.-.-| ----------------------------------------------------------------- opcode Rd Rs1 Rs2 \ operation /
Rd <- Rs1 op Rs2
Time: -1 0 1 2
+-----+
Iaddr: | |
+-----+-----+
Fetch: | RR |
+-----+-----+
Compute: | op |
+-----+
Rd is changed at time 2, and Rs1 and Rs2 are their
values after time 1.
`F' determines whether the instruction modifies (1) or does not modify (0) the program flags.
`BBB' determines the operation: add (000), addc
(001), sub (010), subb (011), and (100), or
(101), xor (110), or special (111). The `JJJJJ' field
is irrelevant except for special.
`JJJJJ' determines which special operation is performed.
10--- is a logical shift, and 11--- is an arithmetic
shift. The amount and direction of the shift are determined by the
contents of Rs2 interpretted as a two's complement number (in the
same way as shifts in the Register-Immediate instructions in section Register Immediate (RI)).
All other `JJJJJ' combinations are reserved for instructions that
may be defined in the future.
If the `F' bit is 1, RR instructions modify the condition bits,
`Z' (Zero), `N' (Negative), `V' (oVerflow), and `C'
(Carry), according to the result. All RR instructions modify the
`Z', `N', and `V' flags. Except for arithmetic
instructions (add, addc, sub, subb),
`V' is cleared. Only arithmetic instructions and shifts modify
`C'. Right shifts clear C.
A Jump is accomplished by Rd being pc, and it has
one shadow.
----------------------------------------------------------------- |1.1.0.1| . . . . | . . . . |F.H| . . . . |A.A.A| . . . . |C.C.C| ----------------------------------------------------------------- opcode Rd Rs1 Rs2 op2 Rs3 op1
Rd <- Rs1 op2 (Rs2 op1 Rs3)
Time: -1 0 1 2
+-----+
Iaddr: | |
+-----+-----+
Fetch: | RRR |
+-----+-----+
Compute: |op op|
+-----+
This instruction is similar to Register-Register (see section Register Register (RR)), except
that the right operand is computed as (Rs2 op1 Rs3) and Rd
may not be 2 (pc) or 31 (isr). It is performed in one
time step.
Rd is changed at time 2, and Rs1, Rs2, and
Rs3 are their values after time 1.
Rd may not be 2 (pc) or 31 (isr).
`F' determines whether the instruction modifies (1) or does not modify (0) the program flags.
`AAA' determines the second operation (op2) in the same
format as the RI instruction: add (000), addc (001),
sub (010), subb (011), and (100), or (101),
xor (110), or shift (111), and the result modifies the
condition bits in the same way as the RI and RR instructions. For the
shift, `H' determines a logical (0) or arithmetic (1) shift just as
in the RI instruction, and the right operand determines the amount and
direction of the shift in the same format as the RI and RR instructions.
`CCC' determines the first operation (op1): add (000),
addc (001), sub (010), subb (011), and (100),
or (101), xor (110), or sha (arithmetic shift) (111).
A Jump is accomplished by Rd being pc, and it has one shadow.
----------------------------------------------------------------- |1.0.0.S| . . . . | . . . . |P.Q| . . . . . . . . . . . . . . . | ----------------------------------------------------------------- opcode Rd Rs1 constant (16)
Rd <- Memory(ea) (Load) see below for the Memory(ea) <- Rd (Store) definition of ea.
Time: -1 0 1 2 3
+-----+
Iaddr: | |
+-----+-----+
Fetch: | RM |
+-----+-----+
Compute: | ea | (compute the effective address)
+-----+-----+
Memory: | r/w |
+-----+
`S' determines whether the instruction is a Load (0) or a Store (1).
Depending on `S', Rd or Memory contents is changed at time
3, and Rs1 is its value after time 1. If Rs1 is changed,
the change occurs at time 2. On a store, the value of Rd written
to memory is the value after time 1. In other words, loads have a
shadow, but stores do not.
PQ operation -- ------------------------------------------ 00 ea = Rs1 01 ea = Rs1, Rs1 <- Rs1 + constant 10 ea = Rs1 + constant 11 ea = Rs1 + constant, Rs1 <- Rs1 + constant
The constant is sign-extended for this instruction.
Rd may not be 2 (pc) or 31 (isr).
A Jump is accomplished by Rd being pc, and it has
two shadows.
----------------------------------------------------------------- |1.0.1.S| . . . . | . . . . |P.Q| . . . . |B.B.B|J.J.J.J.J|Y.L.E| ----------------------------------------------------------------- opcode Rd Rs1 Rs2 \ operation /
Rd <- Memory(ea) (Load) see below for the Memory(ea) <- Rd (Store) definition of ea.
Time: -1 0 1 2 3
+-----+
Iaddr: | |
+-----+-----+
Fetch: | RRM |
+-----+-----+
Compute: | ea | (compute the effective address)
+-----+-----+
Memory: | r/w |
+-----+
The RRM instruction is identical to the RM (see section Register Memory (RM)) instruction
(including the fact that Rd may not be 2 (pc) or 31
(isr)) except that
Rs1 + constant is replaced with
Rs1 op Rs2, where op is determined in the same way as in
the RR instruction (see section Register Register (RR)) and
If `BBB' != 111 (i.e.: For all but shift operations):
If `YLE' = 01- => fuLl-word memory access
If `YLE' = 00- => half-word memory access
If `YLE' = 10- => bYte memory access
If `YLE' = --1 => loads are zEro extended
If `YLE' = --0 => loads are sign extended
If `BBB' = 111 (For shift operations):
fullword memory access are performed.
All part-word loads write the least significant part of the destination register with the higher-order bits zero- or sign-extended. All part-word stores store the least significant part-word of the source register in the destination memory location.
A Jump is accomplished by Rd being pc, and it has
two shadows.
----------------------------------------------------------------- |1.1.1.0|D.D.D| . . . . . . . . . . . . . . . . . . . . . . |R.I| ----------------------------------------------------------------- opcode condition constant (23)
`R' = 0:
if (condition) { pc <- 4*(zero-extended constant) }
`R' = 1:
if (condition) { pc <- pc + 4*(sign-extended constant) }
Time: -1 0 1 2
+-----+
Iaddr: | |
+-----+-----+
Fetch: | BR |
+-----+-----+
Compute: | add |
+-----+
`R'=0 specifies an absolute branch and `R'=1 specifies a relative branch. The constant is scaled as shown by its position in the instruction word such that it specifies word-aligned addresses in the range [0,2^25-4] if `R'=0 or the range [-2^24,2^24-4] if `R' = 1.
The condition after time 1 determines whether the pc is changed
at time 2. For a relative branch that is taken, the value of R2
after time 1 is added to the scaled and sign-extended constant. One
instruction fetched after the BR is always executed before
execution resumes at the location specified by the branch
instruction. That is, the branch has one shadow.
The `DDDI' field selects one of the following logical functions of
the flags (the I (Invert sense) bit inverts the sense of the
condition):
DDDI logical function [code, used for...] ---- -------------------------------------- ------------------------ 0000 1 [T, true] 0001 0 [F, false] 0010 C AND Z' [HI, high] 0011 C' OR Z [LS, low or same] 0100 C' [CC, carry cleared] 0101 C [CS, carry set] 0110 Z' [NE, not equal] 0111 Z [EQ, equal] 1000 V' [VC, oVerflow cleared] 1001 V [VS, oVerflow set] 1010 N' [PL, plus] 1011 N [MI, minus] 1100 (N AND V) OR (N' AND V') [GE, greater than or equal] 1101 (N AND V') OR (N' AND V) [LT, less than] 1110 (N AND V AND Z') OR (N' AND V' AND Z') [GT, greater than] 1111 (Z) OR (N AND V') OR (N' AND V) [LE, less than or equal]
----------------------------------------------------------------- |1.1.1.1.-.-.-.-.-.-.-.-.-.-.1.1.1.1.1.1.1.1.1.1.-.1.-.-.-.1.1.1| -----------------------------------------------------------------
Toggles the context.
The timing is the same as for the RI (see section Register Immediate (RI)) instruction. The PUNT instruction switches execution to the alternate context. This instruction has no shadow. The context switch occurs as described in section Dual-Context Operation, with the switch occuring after the PUNT instructions is actually executed (the "Compute" pipeline stage).
----------------------------------------------------------------- |1.1.1.1| . . . . | . . . . |0.S| . . . . . . . . . . . . . . . | ----------------------------------------------------------------- opcode Rd addr 5msb's address 16 lsb's
If S = 0 (LOAD): Rd <- Memory(address); If S = 1 (STORE): Memory(address) <- Rd
The timing is the same as for RM (see section Register Memory (RM)) and RRM (see section Register Register Memory (RRM)) instructions. The two low-order bits of the 21-bit address are ignored. The address is zero extended. Fullword memory accesses are performed.
Rd may not be 2 (pc) or 31 (isr).
----------------------------------------------------------------- |1.1.1.1| . . . . | . . . . |1.0| . . . . . . . . . . . . . . . | ----------------------------------------------------------------- opcode Rd const 5msb's constant 16 lsb's
Rd <- constant
The 21-bit constant is zero-extended. The timing is the same as the RM instruction (see section Register Memory (RM)).
----------------------------------------------------------------- |1.1.1.1| . . . . | . . . . |1.1.0.Y.S.E.P.Q| . . . . . . . . . | ----------------------------------------------------------------- opcode Rd Rs1 constant
If `YS' = 11 (bYte Store):
Memory(ea) <- (least significant byte of Rr)
If `YS' = 01 (halfword Store):
Memory(ea) <- (least significant half-word of Rr)
If `YS' = 10 (bYte load): Rr <- Memory(ea)
If `YS' = 00 (halfword load): Rr <- Memory(ea)
[Note: here ea is determined as in the the RM instruction. ]
If `SE' = 01 then the value is zEro extended
before being loaded into Rd.
If `SE' = 00 then the value is sign extended
before being loaded into Rd.
`P' and `Q' are used to determine ea as in the RM
instruction. The constant is sign extended. The timing is the same as
the RM and RRM instructions. See section Register Memory (RM) and section Register Register Memory (RRM).
Rd may not be 2 (pc) or 31 (isr).
All part-word loads write the part-word into the least significant part of the destination register, with the higher-order bits zero- or sign-extended. All part-word stores store the least significant part-word of the source register into the destination memory location.
----------------------------------------------------------------- |1.1.1.1|D.D.D|-.-| . . . . |1.1.1.1.0.0.0.0.0.0|-.-.-.-.-|0.0.I| ----------------------------------------------------------------- opcode Rs1 Rs3
pc <-conditionally- Rs1 add Rs3
"pc <-conditionally-" means the pc is modified if and
only if the condition specified by `DDDI' is satisfied, as in the
BR instruction (see section Conditional Branch (BR)). The timing is the same as in the
BR instruction.
WARNING: The SBR instruction is experimental and may not be supported in future versions of the chip.