Documentation for serial links used on Xbar16 --------------------------------------------- port scan order: for writing: port0, port1, ... , port15 for reading: port0, port1, ... , port15 so, data input pin connects to port15's register, output comes from port0's register For information not contained in this document (chip id register, protocol, pins, etc.) see the serial link general information documentation. Addresses and format of serial chains ------------------------------------- The Xbar16 currently has 8 serial chains defined. AAAAAA | 543210 | chain name -------+------------------------ 000000 | chip id register 000001 | impedence test register 000010 | impedence register(*) 000011 | speed control register (**) 000100 | packet and CRC counters 000101 | link status register 000110 | link control register 000111 | global control register * - see below for special use of slat- during impedence register writes. ** - writes to the speed control register will block the channels. See the general information document. The information is listed under writes to the impedence register, since previous chips blocked during writes to the impedence register. Slat-, at the end of a write to the impedence register, must go a high, then low, then high again to properly latch the new impedence value into the chip. The time between each transition should be about one microsecond. Writes to the impedence register will no longer block the channels during this time. Writes to invalid addresses are ignored, reads from invalid addresses will return 0. Chip id register - address 000000 --------------------------------- See the serial link general information documentation for more information. Impedence test register - address 000001 ---------------------------------------- This register has 2 bytes. It is read/write. This register sets the output impedence of OAH and OAL. It is intended that the external controller use this register to "test" an output impedence before modifying the impedence register. This register has no effect when the on-chip impedence control circuitry is enabled (i.e. when the scanz bit in the gctrl register is 0) Byte #1: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | | | | | | | | | | not | pull-up impedence for OAH | not | | used | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 | used | +---------------------------------------------------------------+ rs: 1 1 1 0 0 0 0 1 Byte #2: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | | | | | | | | | | not | pull-down impedence for OAL | not | | used | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 | used | +---------------------------------------------------------------+ rs: 1 1 1 0 0 0 0 1 Impedence register - address 000010 ----------------------------------- This register has 2 bytes. It is read/write. This register sets the output impedence of the channel outputs. It is intended that the external controller try out new impedences in the impedence test register before writing them to this register. Note that this register has special requirements for the slat- signal (see protocol section of the general information document). This register has no effect when the on-chip impedence control circuitry is enabled (i.e. when the scanz bit in the gctrl register is 0) Byte #1: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | | | | | | | | | | not | pull-up impedence | not | | used | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 | used | +---------------------------------------------------------------+ rs: 1 1 1 0 0 0 0 1 Byte #2: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | | | | | | | | | | not | pull-down impedence | not | | used | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 | used | +---------------------------------------------------------------+ rs: 1 1 1 0 0 0 0 1 Speed control register - address 000011 --------------------------------------- This register has 4 bytes. It is read/write. This register controls, on a port by port basis, whether it uses the cfast pin or the cslow pin as a reference clock. The control for the transmitter and receiver is independent. Byte #1: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | port7 | port6 | port5 | port4 | port3 | port2 | port1 | port0 | | rec | rec | rec | rec | rec | rec | rec | rec | | fast | fast | fast | fast | fast | fast | fast | fast | +-------+-------+-------+-------+-------+-------+-------+-------+ rs: 0 0 0 0 0 0 0 0 Byte #2: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | port7 | port6 | port5 | port4 | port3 | port2 | port1 | port 0| | xmit | xmit | xmit | xmit | xmit | xmit | xmit | xmit | | fast | fast | fast | fast | fast | fast | fast | fast | +-------+-------+-------+-------+-------+-------+-------+-------+ rs: 0 0 0 0 0 0 0 0 Byte #3: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | port15| port14| port13| port12| port11| port10| port9 | port8 | | rec | rec | rec | rec | rec | rec | rec | rec | | fast | fast | fast | fast | fast | fast | fast | fast | +-------+-------+-------+-------+-------+-------+-------+-------+ rs: 0 0 0 0 0 0 0 0 Byte #4: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | port15| port14| port13| port12| port11| port10| port9 | port8 | | xmit | xmit | xmit | xmit | xmit | xmit | xmit | xmit | | fast | fast | fast | fast | fast | fast | fast | fast | +-------+-------+-------+-------+-------+-------+-------+-------+ rs: 0 0 0 0 0 0 0 0 portX rec fast: if 1, port X's receiver uses cfast as frequency reference. if 0, uses cslow as frequency reference. portX xmit fast: if 1, port X's trasmitter uses cfast as frequency reference. id 0, uses cslow as frequency reference. Packet and CRC counters - address 000100 ---------------------------------------- This register has 4 bytes per port. It is read only. When this register is read, the contents of the counters are loaded into the shift register. The counters are not cleared on a read, so all counts are cumulative. Each counter is 16 bits wide, and so will rollover after 65536 counts. The bad counter counts packets with incorrect CRCs, the good counter counts packets with correct CRCs. Each port: Byte 4N+1#: (N = port number, starting from 0) MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | | | | | | | | | | bad CRC counter | | bit 15| bit 14| bit 13| bit 12| bit 11| bit 10| bit 9 | bit 8 | +---------------------------------------------------------------+ rs: 0 0 0 0 0 0 0 0 Byte 4N+2#: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | | | | | | | | | | | | bad CRC counter | | | | bit 7 | bit 6 | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 | +---------------------------------------------------------------+ rs: 0 0 0 0 0 0 0 0 Byte 4N+3#: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | | | | | | | | | | good CRC counter | | bit 15| bit 14| bit 13| bit 12| bit 11| bit 10| bit 9 | bit 8 | +---------------------------------------------------------------+ rs: 0 0 0 0 0 0 0 0 Byte 4N+4#: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | | | | | | | | | | | | good CRC counter | | | | bit 7 | bit 6 | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 | +---------------------------------------------------------------+ rs: 0 0 0 0 0 0 0 0 Link Status Register - address 000101 ------------------------------------- This register has 16 bits per port. It is read only. This register provides status on the link. A "*" means that the bit is reset-on-read (ROR). See Reset-On-Read section, below. A "!" means that the bit is negative logic. (The idea is, wherever possible, to make 1 the error condition and 0 the normal condition). The scan order is sixteen 12-bit segments for the receive ports, followed by 16 4-bit segments for the transmit ports Bits 12*N to 12*N+7: (bits are numbered starting at 0, N == port number) 0 1 2 3 4 5 6 7 +-------+-------+-------+-------+-------+-------+-------+-------+ | | miss | !no | port | !rec | !gap | | | | ill | 3 | beat | off | in | rcvd* | inv | data | | rcvd* | beat* | rcvd* | | go* | | head* | in | +-------+-------+-------+-------+-------+-------+-------+-------+ rs: 0 1 1 0 1 1 0 0 description: ill rcvd: set when an illegal symbol is received. If illegal symbol shutdown is enabled (see link control register) the port will be brought down. This bit is reset on read (*). miss 3 beat: set if no beat is received for 3 bclk times. If missing beat shutdown is enabled (see link control register) the port will be brought down. This bit is reset on read (*). port off: will be set to 1 if the port is disabled due to an illegal symbol being received or 3 beats being missed. This bit is cleared by disabling the illegal symbol/missing beats shutdowns. This bits's state is undefined when this port's on-chip link control circuitry is enabled (i.e. the auto en bit for this port in the control register is high). !no beat rcvd: set to 0 when a beat is received. Will reset to 1 on read. (*) !rec in go: set to 0 when receiver is in GO. Will reset to 1 on read. (*) !gap rcvd: set to 0 when a GAP is received. Will reset to 1 on read. (*) inv head: set to 1 when a packet with an invalid head byte is received. Will reset to 0 on read. (*) NOTE: one byte packets are not treated as having head bytes, and so will not set this bit. A one byte packet will increment the good CRC counter if zero, the bad CRC counter if nonzero. data in: set to 1 when a data flit arrives. Will reset to 0 on read. (*) Bits 12*N+8 to 12*N+11: 8 9 10 11 +-------+-------+-------+-------+ | auto | auto | | | | port | rec | not | not | | off | to | used | used | +-------+-------+-------+-------+ rs: 0 0 0 0 Note: the following two bits are valid only if the auto en bit for this port in the control register is set. Otherwise, these bits' states are undefined. auto port off: This bit indicates the port's present state. 0 indicates on, 1 indicates off. auto rec to: This bit indicates if the port's input has timed out (either by blocking too long or by going too long between receiving GAPs). bits 12*16+4*N to 12*16+4*N+3: (N = port number) 0 1 2 3 +-------+-------+-------+-------+ | !xmit | !xmit | | auto | | send | in | data | xmit | | gap* | go* | out | to | +-------+-------+-------+-------+ rs: 0 0 0 0 !xmit send gap: set to 0 when a GAP is sent. Will reset to 1 on read. (*) !xmit in go: set to 0 when transmitter is in go. Will reset to 1 on read. (*) data out: set to 1 when a data flit is transmitted. Will reset to 0 on read. (*) auto xmit to: This bit indicates if the port's output has timed out (either by blocking too long or by going too long between receiving GAPs). This bit is valid only if the auto en bit for this port in the control register is set. Otherwise, this bit's state is undefined. Reset On Read ------------- This name is somewhat misleading, it should actually be called "Reset on 2 reads". Due to the asynchronous nature of events on the SAN link, some imprecision in the reset-on-read functionality has to be tolerated. It was judged better to report a single event multiple times than to ever miss an event. So, most of the time, it will take 2 reads to clean a ROR (reset on read) bit. A small fraction of the time a bit will clear after only 1 read. The ROR is implemented as follows: +----+ in ---+-----|S | | | Q|----+ | +-|R | | | | +----+ | | | | | | +----+ | +----+ +-----|S | +-| | | | | Q|------| OR |----> to shift register bit | +---|R | +-| | | | | +----+ | +----+ | | | | | | | +----+ | +-----|S | | | | | Q|----+ +-----|R | | | | +----+ | | | | | | +---------+ | A B C | | | <- reset generator +---------+ The reset generator generates a pulse on one of A, B, or C before each read. On the 3rd read of the bit, all 3 flip-flops will have been cleared, so an input event will normally cause the ouput to be high for only 2 reads (all 3 flip flops are cleared by the 3rd read). If the input stays high or is triggered continuously, the bit will continue to read as 1 until the input has been low for at least one read. Link Control Register - address 000110 -------------------------------------- This register has 1 byte per port. It is read/write. This register controls turning the port on/off and handles the enabling of port shutdown after illegal symbol or missing beat. Byte #N+1: (N = port number, starting at zero) MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | xmit | rec | miss | ill | | auto | | | | off | off | beat | sd | auto | ha | not | not | | | | sd en | enable| en | en | used | used | +-------+-------+-------+-------+-------+-------+-------+-------+ rs: 1 1 0 0 (!) (!!) 0 0 (!) - The reset state of the auto en bit is determined by the ae pin. See the auto en description below for more information. (!!) - The reset state of the auto ha en bit is determined by the ahae pin. See the auto ha en desctiption below for more information. Note: The xmit off, rec off, miss beat sd en, and ill sd enable bits have effect only if the auto en bit is 0. Otherwise, they are ignored. xmit off: If 1, turns sender off, if 0, turns sender on. rec off : If 1, turns receiver off, if 0, turns receiver on. miss beat sd en: "Missing beat shutdown enable" If 1, port will shutdown if no beat received for 3 bclk cycles. If 0, missing 3 beats is ignored. ill sd enable: "Illegal symbol shutdown enable" If 1, port will shutdown if an illegal symbol is received. If 0, illegal symbols are ignored. auto en: If 1, all link control for this port will be handled by the xbar16. If 0, all link control must be handled through the scan path. This bit will reset to 0 if the aen pin is low during chip reset. It will reset to 1 if the aen pin is high during chip reset. auto ha en: if 1, the port will require BEATs to turn on, and the port will turn off if illegal symbols are received. If 0, the port will not require BEATs to turn on, and will ignore illegal symbols if received. If the auto en bit is 0, this bit has no effect. This bit will reset to 0 if the aha pin is low during chip reset. It will reset to 1 if the aha pin is high during chip reset. Note: The following note applies only if the auto en bit is 0. Note on xmit off and rec off bits: If the xmit off and/or rec off bits were 0, the shutdown enables are 1, and the port is shutdown for an illegal symbol or missing beat, the xmit off and rec off bits will still read 0. These bits are controlled by the external controller only. To see if the port is on or off, one must read the port off bit in the link status register. The recommended procedure following port shutdown from illegal symbol/missing beats is to: 1) With one write to the link control register, set the xmit off and rec off bits, leaving the shutdown enable bits set. 2) With another write, leave the xmit off and rec off bits set, while clearing the shutdown enable bits. This will clear the illegal symbol/missing beat shutdown while keeping the port off. 3) With yet another write, reenable the illegal symbol/missing beat shutdowns. One can then observe the port_off bit or the illegal symbol rec'd/missing beat in the link status register to see if the link returns to normal. If the port again encounters an illegal symbol/missing beat, go back to step #2 4) Once the port has been well behaved for a sufficient time, one can write the xmit off and rec off bits back to 0 to resume normal port operation. Global Control - address 000111 ------------------------------- This register is 1 byte, and is read/write. It handles some global configuration details. Byte #1: MSB LSB +-------+-------+-------+-------+-------+-------+-------+-------+ | | | | | time | time | | | | win1 | win0 | fast | fast | out | out | not | scanz | | | | win1 | win0 | bit 1 | bit0 | used | | +-------+-------+-------+-------+-------+-------+-------+-------+ rs: 1 1 1 1 1 1 0 0 win1, win0 : Sets receiver sampling window. Should be 11. fast win1, fast win0: sets the receiver sample window when a port is set to "fast". Should be 11. scanz: controls whether the scan path sets the output impedence or not. If 0, the on-chip impedence control circutry is enabled, and the scan path impedence registers are ignored. If 1, the on-chip impedence control is disabled, and the scan path impedence registers are used instead. This bit affects both the output impedence register and the output impedence test register. Timeout bit0,1: Sets the timeout period for the on-chip link control. The timeouts are as follows: timeout bit 1 | 0 | resulting timeout --------------+---+------------------ 0 | 0 | 1/16 sec 0 | 1 | 1/4 sec 1 | 0 | 1 sec 1 | 1 | 4 sec The timeout period for the HA features is always 1/4 sec. If 1/4 second goes by and there are no missed beats or illegal symbols, the port will be brought up. If a beat is missed or an illegal symbol is received, the port is shut down in less than 30 microseconds.