General Information for Myrinet Low Level Management Links
----------------------------------------------------------

Protocol
--------

The low level management link is a bidirectional serial link, used to monitor
and control certain features of a Myrinet chip. All Myrinet chips are
slave-only devices, i.e. they never initiate a transfer. The link uses 4 pins.
They are:

sclk  - used to clock data in and out. Data is latched on rising edges of sclk.
sdi   - data into chip
sdo   - data out of chip. The data changes after falling edges of sclk.
slat- - used to frame serial transactions

Since Myrinet components are slave only, sclk, sdi, and slat- are always
inputs, and sdo is always an output. At the present time, sdo's output buffer
is always active (no tri-state). 

The data is generally shifted MSB first. A serial transaction has two phases.
During the first phase, the command byte is shifted in. It indicates whether a
read or write is to take place, and which serial chain is to be accessed. The
second phase shifts the read/write data out of/into the chip. The first phase
looks like this:
      __                                                   
slat-   \__________________________________________________
            __    __    __    __    __    __    __    __   
sclk ______/1 \__/2 \__/3 \__/4 \__/5 \__/6 \__/7 \__/8 \__
     ________________ _____ _____ _____ _____ _____ _____ _
sdi  ____/ *  \_W/R-_X__A5_X__A4_X__A3_X__A2_X__A1_X__A0_X_

* ==> data for first bit must be high. Leading low bits are ignored. This may
be useful if the microcontroller in use can only send multiples of 16 bits. In
that case, the first 8 bits should be low, the last 8 bits should hold the
desired command byte.

The second phase is shown below for both reads and writes. If W/R- is 0, sdi
is "don't care", sdo will become valid after the 8th falling edge of sclk. If
W/R- is 1, sdo will be 0.
                                       _______
slat- ___________________ ... ________/
        __    __    __           __
sclk  _/8 \__/9 \__/10\__ ... __/N \__________
            _____ _____ _      _______________ 
sdo   _____/__O7_X__O6_X_ ... X__ON___________  (if read)
      _____ _____ _____ _      _______________
sdi   __A0_X__I7_X__I6_X_ ... X__IN___________  (if write)

During reads, the data is transferred into the shift register after the 8th
falling edge of sclk. During writes, the data is transferred to storage
registers after the rising edge of slat.

There is one special case, involving the impedence register. In order to
prevent impedence changes when the channel is active, a special protocol is
used for latching data into that register:
    
        data transferred here (impedence changes)
                         |
                 ________V         ________
slat- ... ______/        \________/
            __
sclk  ... _/N \____________________________
          _________________________________
sdi   ... _IN______________________________
                 _________________
STOP  ... ______/                 \________
(internal signal, 
 holds transmitter and receiver in STOP mode)

Slat should be high for >=0.4usec and low for >=0.4usec. Excessive high or low
times will affect network performance. High or low times much longer than 10
microseconds will interfere with the link-continuity monitoring.

Note: If sclk will make transistions when slat- is high, the same sort of pulse
must be applied after every access to avoid corruption of the internal data.
Writes to all other registers will NOT block the channels regardless of the
behavior of slat-.

Addressing
----------

The 6 address bits provide for up to 64 serial chains. Unused addresses will
typically read as 0, and data written to unused addresses will be ignored.

The assignment of addresses to functions varies from chip to chip. However all
chips have an id register at adress 000000. This document covers only the id
register; for all other register information, consult the serial link document
for the particular chip.

Chip id register - address 000000
---------------------------------

This register has 2 bytes. This register is read only, writes are ignored.

Byte #1:
     MSB                                                     LSB
  +-------+-------+-------+-------+-------+-------+-------+-------+
  |       |       |       |       |       |       |       |       |
  |   chip type   |            chip subtype (6 bits)              |
  |   (2 bits)    |                                               |
  +-------+-------+-------+-------+-------+-------+-------+-------+  

  chip type = 00 for LANai
            = 01 for Xbar
            = 100 for MI (uses top bit of subtype, too)
            = 101 for FI (uses top bit of subtype, too)
            = 11 reserved for future expansion

  chip subtype = 000110 (6) for LANai 6
                 010000 (16) for xbar 16
                  00011 (3) for MI3
                  00010 (2) for FI2
Byte #2:
     MSB                                                     LSB
  +-------+-------+-------+-------+-------+-------+-------+-------+
  |       |       |       |       |       |       |       |       |
  |      revision # (4 bits)      |        run # (4 bits)         |
  |                               |                               |
  +-------+-------+-------+-------+-------+-------+-------+-------+

revision: 0000 for all X.0 chips
          0001 for all X.1 chips, etc.
          Note: revision # only changes when serial interface changes,
                so revision number may not match actual chip revision #.

run: not presently used (always 0000).


chips and their ID register values:

L6.0:  06 00
L6.1:  06 10
L7.0:  06 03
LANSAN3.0: 83 00
LANSAN3.1: 83 10
FI2.0: A2 00
FI2.1: A2 00